Datasheet

Rev. 4.00 Jun 06, 2006 page ix of liv
Item Page Revision (See Manual for Details)
16.4 Usage Notes 514 to
521
• Notes on WAIT Function
• Notes on ICDR Reads and ICCR Access in Slave Transmit
Mode
• Notes on TRS Bit Setting in Slave Mode
• Notes on Notes on Arbitration Lost in Master Mode
• Notes on Interrupt Occurrence after ACKB Reception
Description added
17.1.3 Input and Output
Pins
Table 17.1 Host
Interface Input/Output
Pins
525 Note * amended
Note: * Selection of CS2 or ECS2 is by means of the CS2E
bit in S
YSCR and ...
19.4.3 Input Sampling
and A/D Conversion
Time
Figure 19.5 A/D
Conversion Timing
566 Figure 19.5 amended
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
19.6 Usage Notes
Figure 19.11 Example
of Analog Input Circuit
572 Note added
Note: Values are reference values.
21.5.2 Flash Memory
Control Register 2
(FLMCR2)
590 Description amended
Bits 6 to 2Reserved:
Always write 0 when writing to these
bits.
21.6.1 Boot Mode 597 Description amended
... H'(FF)E080 to H'(FF)EFFF (3968 bytes) in the 128-kbyte
versions
including H8S/2132, except for H8S/2132R or
H'(FF)E880 to H'(FF)EFFF (1920 bytes) in the 64-kbyte
versions including H8S/2132R, except for H8S/2132.