Datasheet

Appendix C I/O Port Block Diagrams
Rev. 4.00 Jun 06, 2006 page 991 of 1004
REJ09B0301-0400
D
R
QD
P86DR
C
Reset
R
Q
P86DDR
C
Reset
WP8D
*1
*2
WP8
SCI1
Input enable
Clock output
SCL1 output
SCL1 input
IRQ5 input
IRQ5 enable
Transmit enable
Output enable
Clock input
IIC1
P86
RP8
Legend:
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Notes: 1. Output enable signal
2. Open drain control signal
Internal data bus
Hardware
standby
Figure C.28 Port 8 Block Diagram (Pin P86)