Datasheet

Appendix C I/O Port Block Diagrams
Rev. 4.00 Jun 06, 2006 page 979 of 1004
REJ09B0301-0400
D
R
QD
P52DR
C
Reset
R
Q
P52DDR
C
Reset
WP5D
*
1
*
2
WP5
SCI0
Input enable
Clock output
SCL0 output
SCL0 input
Transmit enable
Output enable
Clock input
IIC0
P52
RP5
Legend:
WP5D: Write to P5DDR
WP5: Write to port 5
RP5: Read port 5
Notes: 1. Output enable signal
2. Open drain control signal
Internal data bus
Hardware
standby
Figure C.15 Port 5 Block Diagram (Pin P52)