Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 958 of 1004
REJ09B0301-0400
IDR1—Input Data Register 1 H'FFF4 HIF
IDR2—Input Data Register 2 H'FFFC HIF
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
Bit
Initial value
Slave R/W
Host R/W
Stores host data bus contents at rise of IOW when CS is low
ODR1—Output Data Register 1 H'FFF5 HIF
ODR2—Output Data Register 2 H'FFFD HIF
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
Bit
Initial value
Slave R/W
Host R/W
ODR contents are output to the host data bus
when HA0 is low, CS is low, and IOR is low
TISR—Timer Input Select Register H'FFF5 TMRY
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IS
0
R/W
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
Input select
0
1
IVG signal is selected (H8S/2138 Group)
External clock/reset input is disabled (H8S/2134 Group)
VSYNCI/TMIY (TMCIY/TMRIY) is selected