Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 20 MHz I/O number 58

Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 954 of 1004

REJ09B0301-0400

HICR—Host Interface Control Register H'FFF0 HIF

7

—

1

—

—

6

—

1

—

—

5

—

1

—

—

4

—

1

—

—

3

—

1

—

—

0

FGA20E

0

R/W

—

2

IBFIE2

0

R/W

—

1

IBFIE1

0

R/W

—

Bit

Initial value

Slave R/W

Host R/W

Fast gate A20 enable

0 Fast gate A20 function

disabled

1 Fast gate A20 function

enabled

Input data register interrupt enable 1

0 Input data register (IDR1)

receive complete interrupt is

disabled

1 Input data register (IDR1)

receive complete interrupt is

enabled

Input data register full interrupt enable 2

0 Input data register (IDR2) receive complete

interrupt is disabled

1 Input data register (IDR2) receive complete

interrupt is enabled