Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 953 of 1004
REJ09B0301-0400
TCSR1—Timer Control/Status Register 1 H'FFEA WDT1
7
OVF
0
R/(W)
*
1
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
TCSR1
Clock select 2 to 0
PSS
0
1
ClockCKS2
0
1
0
1
CKS1
0
1
0
1
0
1
0
1
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes: 1.
2.
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Reset or NMI
0
NMI interrupt requested
1 Internal reset requested
Prescaler select
*
2
0 TCNT counts on a φ-based prescaler (PSM) scaled clock
1 TCNT counts on a φSUB-based prescaler (PSS) scaled clock
Timer enable
0
TCNT is initialized to H'00 and halted
1 TCNT counts
Timer mode select
0
Interval timer mode: Interval timer interrupt request (WOVI)
sent to CPU when TCNT overflows
1 Watchdog timer mode: Reset or NMI interrupt request sent
to CPU when TCNT overflows
Overflow flag
0
[Clearing conditions]
• When 0 is written in the TME bit
• When 0 is written in OVF after reading TCSR when OVF = 1
1 [Setting condition]
When TCNT overflows from H'FF to H'00
When internal reset request is selected in watchdog timer mode, OVF is cleared
automatically by an internal reset after being set
Only 0 can be written, to clear the flag.
For operation control when a transition is made to power-down mode, see section 24.2.3, Timer Control/Status Register (TCSR).