Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 945 of 1004
REJ09B0301-0400
TCSR1—Timer Control/Status Register 1 H'FFCB TMR1
7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
0
R/(W)
*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSR1
Output select 1 and 0
0 No change at compare match A
0
0 output at compare match A1
1 1 output at compare match A0
Output inverted at compare
match A (toggle output)
1
Output select 3 and 2
0 No change at compare match B
0
0 output at compare match B1
1 1 output at compare match B0
Output inverted at compare
match B (toggle output)
1
Timer overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Compare match flag A
0 [Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
1 [Setting condition]
When TCNT = TCORA
Compare match flag B
0 [Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
1 [Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written in bits 7 to 5, to clear the flags.