Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 20 MHz I/O number 58

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas

Electronics Corporation took over all the business of both

companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (1063 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
PAGE 2
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
PAGE 3
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
PAGE 4
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
PAGE 5
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
PAGE 6
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6 Overview 7.
PAGE 7
Preface The H8S/2138 Group and H8S/2134 Group comprise high-performance microcomputers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen internal 16-bit general registers with a 32-bit configuration, and a concise and optimized instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
PAGE 8
On-Chip Supporting Modules Group H8S/2138 Group H8S/2134 Group Product names H8S/2138, 2137 H8S/2134, 2133, 2132, 2130 Bus controller (BSC) Available (8 bits) Available (8 bits) Data transfer controller (DTC) Available — 8-bit PWM timer (PWM) ×16 — 14-bit PWM timer (PWMX) ×2 ×2 16-bit free-running timer (FRT) ×1 ×1 8-bit timer (TMR) ×4 ×3 Timer connection Available — Watchdog timer (WDT) ×2 ×2 Serial communication interface (SCI) ×3 ×3 I C bus interface (IIC) ×2 (option) —
PAGE 9
Main Revisions for This Edition Item Page Revision (See Manual for Details) All — • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8S/2138 Series → (After) H8S/2138 Group (Before) H8S/2134 Series → (After) H8S/2134 Group Description amended (Before) Serial/timer control register → (After) Serial timer control register 1.3.2 Pin Functions in Each Operating Mode 12 Pin Name Pin No. Table 1.
PAGE 10
Item Page Revision (See Manual for Details) 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform 251 Table amended Upper 4 Bits 0000 Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0001 Table 9.4 Duty Cycle of Basic Pulse 0010 0011 0100 0101 0110 0111 .. . 1000 1001 1010 1011 1100 1101 1110 1111 10.1.3 Pin configuration 255 Channel deleted Table 10.1 Input and Output Pins 12.
PAGE 11
Item Page Revision (See Manual for Details) 16.4 Usage Notes 514 to 521 • Notes on WAIT Function • Notes on ICDR Reads and ICCR Access in Slave Transmit Mode • Notes on TRS Bit Setting in Slave Mode • Notes on Notes on Arbitration Lost in Master Mode • Notes on Interrupt Occurrence after ACKB Reception Description added 17.1.3 Input and Output 525 Pins Table 17.1 Host Interface Input/Output Pins 19.4.
PAGE 12
Item Page Revision (See Manual for Details) 21.6.1 Boot Mode 597 Figure 21.10 amended 1 Programming control* program area (3,968 bytes) Figure 21.10 RAM Areas in Boot Mode Boot program area* (128 bytes) 2 (a) 128-kbyte versions (including H8S/2132) (b) 64-kbyte versions (except for H8S/2132) Note 1 added Note: 1. In H8S/2132 F-ZTAT (Mask ROM version), H'(FF)E080 to H'(FF)E87F is a reserved area that is used only for boot mode operation. Do not use this area for other purpose.
PAGE 13
Item Page Revision (See Manual for Details) 25.2.7 Usage Note 732 Description amended Figure 25.3 Connection of External Capacitor (Mask ROM Type Incorporating Step-Down Circuit and Product Not Incorporating Step-Down Circuit) 25.3.2 DC Characteristics HD6432138S, HD6432138SW, HD6432137S, HD6432137SW, HD6432134S, HD6432133S, HD64F2138A, HD64F2134A 735 Table 25.16 DC Characteristics (1) 736 Table 25.
PAGE 14
Item Page Revision (See Manual for Details) 25.3.2 DC Characteristics 740 Table 25.16 (3) amended Table 25.16 DC Characteristics (3) Item Symbol Min Typ Max Test Unit Conditions Output high All output pins (except P97, and voltage 4 5 P52* )* VOH VCC –0.5 — — V IOH = –200 µA VCC –1.0 — — V IOH = –1 mA 0.5 — — V IOH = –200 µA, VCC = 2.7 to 3.5 V P97, P52* 742 4 Note *4 amended Note: 4. P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs in H8S/2138. ...
PAGE 15
Item Page Revision (See Manual for Details) 25.5.6 Flash Memory Characteristics 797 Table 25.49 amended Item Table 25.49 Flash Memory Characteristics (Programming/Erasing Operating Range) Reprogramming count Data retention time*10 798 Symbol Min 100*8 Typ Max 10000*9 — Times tDRP — Years NWEC 10 — Unit Test Condition Notes 8 to 10 added Notes: 8. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 9.
PAGE 16
Item Page Revision (See Manual for Details) B.
PAGE 17
Item Page Revision (See Manual for Details) B.3 Function 942 WSCR H'FFC7 Bus Controller Figure amended 7 6 RAMS RAM0 Bit Initial value 0 0 Read/Write R/W R/W Reserved Note: Always write 0 when writing to these bits in the A-mask version.
PAGE 18
Item Page Revision (See Manual for Details) Appendix G Package Dimensions 1002 Figure replaced 1003 Figure replaced Figure G.1 Package Dimensions (FP-80A) Figure G.2 Package Dimensions (TFP-80C) Rev. 4.
PAGE 19
Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 7 Pin Arrangement and Functions......................................................................
PAGE 20
2.8.5 Bus-Released State............................................................................................... 2.8.6 Power-Down State ............................................................................................... 2.9 Basic Timing ..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.
PAGE 21
Section 5 Interrupt Controller .......................................................................................... 101 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram ........................................................................
PAGE 22
6.2 6.3 6.4 6.5 6.6 6.7 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration....................................................................................
PAGE 23
7.3 7.4 7.5 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR)........................................................................ 7.2.9 Module Stop Control Register (MSTPCR) .......................................................... Operation ................................................................
PAGE 24
8.6 Port 5................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.2 Register Configuration......................................................................................... 8.6.3 Pin Functions ....................................................................................................... 8.
PAGE 25
9.3.1 Correspondence between PWM Data Register Contents and Output Waveform.......................................................................................... 251 Section 10 14-Bit PWM D/A ........................................................................................... 10.1 Overview........................................................................................................................... 10.1.1 Features......................................................................
PAGE 26
11.3.7 Setting of FRC Overflow Flag (OVF) ................................................................. 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF ......................................... 11.3.9 ICRD and OCRDM Mask Signal Generation ...................................................... 11.4 Interrupts ........................................................................................................................... 11.5 Sample Application.................................................
PAGE 27
12.6.4 Contention between Compare-Matches A and B................................................. 338 12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 338 Section 13 Timer Connection [H8S/2138 Group]...................................................... 341 13.1 Overview........................................................................................................................... 13.1.1 Features.................................................
PAGE 28
14.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 14.4 Interrupts ........................................................................................................................... 14.5 Usage Notes ...................................................................................................................... 14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 14.5.2 Changing Value of CKS2 to CKS0....
PAGE 29
16.1.3 Input/Output Pins ................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 2 16.2.1 I C Bus Data Register (ICDR) ............................................................................. 16.2.
PAGE 30
17.2.9 Status Register 2 (STR2) ..................................................................................... 17.2.10 Module Stop Control Register (MSTPCR) .......................................................... 17.3 Operation .......................................................................................................................... 17.3.1 Host Interface Operation...................................................................................... 17.3.2 Control States............
PAGE 31
19.4.4 External Trigger Input Timing............................................................................. 567 19.5 Interrupts ........................................................................................................................... 567 19.6 Usage Notes ...................................................................................................................... 568 Section 20 RAM ..............................................................................................
PAGE 32
21.9 21.10 21.11 21.12 21.8.1 Hardware Protection ............................................................................................ 21.8.2 Software Protection.............................................................................................. 21.8.3 Error Protection.................................................................................................... Interrupt Handling when Programming/Erasing Flash Memory.......................................
PAGE 33
22.7.1 Program Mode ..................................................................................................... 22.7.2 Program-Verify Mode.......................................................................................... 22.7.3 Erase Mode .......................................................................................................... 22.7.4 Erase-Verify Mode .............................................................................................. Flash Memory Protection.....
PAGE 34
Section 24 Power-Down State ......................................................................................... 681 24.1 Overview........................................................................................................................... 24.1.1 Register Configuration......................................................................................... 24.2 Register Descriptions ........................................................................................................
PAGE 35
25.3 25.4 25.5 25.6 25.2.2 DC Characteristics ............................................................................................... 25.2.3 AC Characteristics ............................................................................................... 25.2.4 A/D Conversion Characteristics........................................................................... 25.2.5 D/A Conversion Characteristics........................................................................... 25.2.
PAGE 36
A.2 A.3 A.4 A.5 Instruction Codes .............................................................................................................. Operation Code Map......................................................................................................... Number of States Required for Execution ........................................................................ Bus States during Instruction Execution ...........................................................................
PAGE 37
Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2138 Group..................................................... 7 Figure 1.2 Internal Block Diagram of H8S/2134 Group..................................................... 8 Figure 1.3 Pin Arrangement of H8S/2138 Group (FP-80A, TFP-80C: Top View) ............ 9 Figure 1.4 Pin Arrangement of H8S/2134 Group (FP-80A, TFP-80C: Top View) ............ 10 Section 2 CPU Figure 2.1 CPU Operating Modes..................................................
PAGE 38
Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 (1) Figure 4.5 (2) Figure 4.6 Reset Sequence (Mode 3) .................................................................................. Reset Sequence (Mode 1) .................................................................................. Interrupt Sources and Number of Interrupts ...................................................... Stack Status after Exception Handling (Normal Mode) ....................................
PAGE 39
Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 7.11 Figure 7.12 Correspondence between DTC Vector Address and Register Information ....... Location of DTC Register Information in Address Space................................. Memory Mapping in Normal Mode .................................................................. Memory Mapping in Repeat Mode.................................................................... Memory Mapping in Block Transfer Mode...............
PAGE 40
Figure 10.4 (3) Output Waveform.............................................................................................. 268 Figure 10.4 (4) Output Waveform.............................................................................................. 268 Section 11 16-Bit Free-Running Timer Figure 11.1 Block Diagram of 16-Bit Free-Running Timer ................................................. Figure 11.2 Input Capture Buffering (Example).................................................................
PAGE 41
Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.14 Figure 12.15 Timing of Input Capture Signal (When Input Capture Input Signal Enters while TICRR and TICRF Are Being Read)....................................................... Switching of Input Capture Signal .................................................................... Pulse Output (Example) .................................................................................... Contention between TCNT Write and Clear ..................
PAGE 42
Figure 15.8 Figure 15.9 Figure 15.10 Figure 15.11 Figure 15.12 Figure 15.13 Figure 15.14 Figure 15.15 Figure 15.16 Figure 15.17 Figure 15.18 Figure 15.19 Figure 15.20 Figure 15.21 Figure 15.22 Figure 15.23 Figure 15.24 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .............................................. Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ......................................
PAGE 43
Figure 16.16 Figure 16.17 Figure 16.18 Figure 16.19 Figure 16.20 Figure 16.21 Figure 16.22 Figure 16.23 Figure 16.24 Figure 16.25 Figure 16.26 Figure 16.27 Flowchart for Slave Receive Mode (Example).................................................. Flowchart for Slave Transmit Mode (Example) ................................................ Points for Attention Concerning Reading of Master Receive Data ................... Flowchart and Timing of Start Condition Instruction Issuance for Retransmission.......
PAGE 44
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Figure 21.1 ROM Block Diagram (H8S/2138, H8S/2134)................................................... Figure 21.2 Block Diagram of Flash Memory ...................................................................... Figure 21.3 Flash Memory Mode Transitions....................................................................... Figure 21.4 Boot Mode..........................................................................
PAGE 45
Figure 22.12 Figure 22.13 Figure 22.14 Figure 22.15 Figure 22.16 Figure 22.17 Program/Program-Verify Flowchart.................................................................. Erase/Erase-Verify Flowchart (Single-Block Erase) ......................................... Flash Memory State Transitions........................................................................ Memory Map in Programmer Mode..................................................................
PAGE 46
Figure 25.9 Figure 25.10 Figure 25.11 Figure 25.12 Figure 25.13 Figure 25.14 Figure 25.15 Figure 25.16 Figure 25.17 Figure 25.18 Figure 25.19 Figure 25.20 Figure 25.21 Figure 25.22 Figure 25.23 Figure 25.24 Figure 25.25 Figure 25.26 Interrupt Input Timing ....................................................................................... Basic Bus Timing (Two-State Access).............................................................. Basic Bus Timing (Three-State Access)................................
PAGE 47
Figure C.18 Figure C.19 Figure C.20 Figure C.21 Figure C.22 Figure C.23 Figure C.24 Figure C.25 Figure C.26 Figure C.27 Figure C.28 Figure C.29 Figure C.30 Figure C.31 Figure C.32 Figure C.33 Port 6 Block Diagram (Pin P64)........................................................................ Port 6 Block Diagram (Pin P66)........................................................................ Port 6 Block Diagram (Pin P67)........................................................................
PAGE 48
Tables Section 1 Overview Table 1.1 Overview ................................................................................................................ 2 Table 1.2 H8S/2138 Group Pin Functions in Each Operating Mode ..................................... 11 Table 1.3 H8S/2134 Group Pin Functions in Each Operating Mode ..................................... 15 Table 1.4 Pin Functions..........................................................................................................
PAGE 49
Section 6 Bus Controller Table 6.1 Bus Controller Pins ................................................................................................ 139 Table 6.2 Bus Controller Registers ........................................................................................ 139 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ........................................ 144 Table 6.4 IOS Signal Output Range Settings .........................................................................
PAGE 50
Section 9 8-Bit PWM Timers [H8S/2138 Group] Table 9.1 Pin Configuration ................................................................................................... Table 9.2 PWM Timer Module Registers .............................................................................. Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz.................................................................................................. Table 9.4 Duty Cycle of Basic Pulse........
PAGE 51
Table 13.9 Meaning of HSYNCO Output in Each Mode......................................................... 367 Table 13.10 Meaning of VSYNCO Output in Each Mode......................................................... 368 Section 14 Watchdog Timer (WDT) Table 14.1 WDT Pin ................................................................................................................ 374 Table 14.2 WDT Registers...................................................................................................
PAGE 52
Table 17.8 Table 17.9 Table 17.10 Table 17.11 Fast A20 Gate Output Signals ................................................................................ Scope of HIF Pin Shutdown in Slave Mode........................................................... Input Buffer Full Interrupts .................................................................................... HIRQ Setting/Clearing Conditions.........................................................................
PAGE 53
Table 21.20 Status Polling Output Truth Table.......................................................................... 620 Table 21.21 Command Wait State Transition Time Specifications ........................................... 620 Table 21.22 Registers Present in F-ZTAT Version but Absent in Mask ROM Version ............ 622 Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.1 ROM Register ..............................................................................
PAGE 54
Table 24.3 Table 24.4 Table 24.5 Power-Down State Registers.................................................................................. 685 MSTP Bits and Corresponding On-Chip Supporting Modules .............................. 694 Oscillation Settling Time Settings.......................................................................... 696 Section 25 Table 25.1 Table 25.1 Table 25.1 Table 25.1 Table 25.2 Table 25.3 Table 25.3 Table 25.3 Table 25.4 Table 25.5 Table 25.6 Table 25.7 Table 25.
PAGE 55
Table 25.25 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) ................................................. Table 25.26 D/A Conversion Characteristics ............................................................................. Table 25.27 Flash Memory Characteristics (Programming/Erasing Operating Range) ............. Table 25.28 Absolute Maximum Ratings................................................................................... Table 25.29 DC Characteristics (1) ...
PAGE 56
Table A.3 Table A.4 Table A.5 Table A.6 Operation Code Map (4) ........................................................................................ Number of States per Cycle.................................................................................... Number of Cycles per Instruction .......................................................................... Instruction Execution Cycle ...................................................................................
PAGE 57
Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2138 Group and H8S/2134 Group comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
PAGE 58
Section 1 Overview Table 1.
PAGE 59
Section 1 Overview Item Specifications Bus controller • 2-state or 3-state access space can be designated for external expansion areas • Number of program wait states can be set for external expansion areas • Can be activated by internal interrupt or software • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc.
PAGE 60
Section 1 Overview Item Specifications 14-bit PWM timer (PWMX) • Up to 2 outputs • Resolution: 1/16384 • 312.5 kHz maximum carrier frequency (20-MHz operation) Serial communication • interface • (SCI: 2 channels, SCI0 and SCI1) Asynchronous mode or synchronous mode selectable • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function • Compatible with IrDA specification version 1.
PAGE 61
Section 1 Overview Item Specifications Memory • Flash memory or mask ROM • High-speed static RAM Interrupt controller Power-down state Product Name ROM RAM H8S/2134, H8S/2138 128 kbytes 4 kbytes H8S/2133 96 kbytes 4 kbytes H8S/2132, H8S/2137 64 kbytes 2 kbytes H8S/2130 32 kbytes 2 kbytes • Nine external interrupt pins (NMI, IRQ0 to IRQ7) • 39 internal interrupt sources • Three priority levels settable • Medium-speed mode • Sleep mode • Module stop mode • Software standby
PAGE 62
Section 1 Overview Item Specifications 3 Product Code* Product lineup (preliminary) Group H8S/2138 Mask ROM Versions F-ZTAT™ Versions ROM/RAM (Bytes) HD6432138S 2 HD64F2138* 128 k/4 k HD6432138SW* HD64F2138A HD6432137S — 64 k/2 k HD6432134S HD64F2134 HD64F2134A 128 k/4 k HD6432133S — 96 k/4 k HD6432132 HD64F2132R 64 k/2 k — 32 k/2 k 1 Packages FP-80A, TFP-80C 1 HD6432137SW* H8S/2134 HD6432130 2 Notes: 1. “W” indicates the I C bus option. 2. FP-80A only 3.
PAGE 63
Section 1 Overview 1.2 Internal Block Diagram VCC1 VCC2 (VCL) VSS VSS VSS An internal block diagram of the H8S/2138 Group is shown in figure 1.1, and an internal block diagram of the H8S/2134 Group in figure 1.2.
PAGE 64
NMI STBY P97/WAIT P96/φ/EXCL Interrupt controller P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD RAM P23/A11 P22/A10 P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 16-bit FRT Port 3 14-bit PWM 8-bit timer × 3ch (TMR0, TMR1, TMRY) 10-bit A/D SCI × 3ch (IrDA × 1ch) 8-bit D/A Port 5 P77/AN7/DA1 P76/AN6/DA0 P75/AN5 Port 7 AVCC AVSS P83 P82 P81 P80 P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 Port 8 P74/AN4 P73/AN3 P72/AN2 P71/AN1
PAGE 65
Section 1 Overview 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement P42/TMRI0/SCK2/SDA1 P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO P45/TMRI1/HIRQ12/CSYNCI P46/PWX0 P47/PWX1 VCC1 P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 VSS P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 The pin arrangement of the H8S/2138 Group is shown in figure 1.3, and the pin arrangement of the H8S/2134 Group in figure 1.4.
PAGE 66
P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 P27/A15 P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 VSS P17/A7 P16/A6 P15/A5 P14/A4 Section 1 Overview A3/P13 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 P41/TMO0/RxD2/IrRxD A2/P12 62 39 P40/TMCI0/TxD2/IrTxD A1/P11 63 38 AVSS A0/P10 64 37 P77/AN7/DA1 D0/P30 65 36 P76/AN6/DA0 D1/P31 66 35 P75/AN5 D2/P32 67 34 P74/AN4 D3/P33 68 33 P73/AN3 D4/P34 69 32 P72/AN
PAGE 67
Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Tables 1.2 and 1.3 show the pin functions of the H8S/2138 Group and H8S/2134 Group in each of the operating modes. Table 1.2 H8S/2138 Group Pin Functions in Each Operating Mode Pin Name Pin No.
PAGE 68
Section 1 Overview Pin Name Pin No.
PAGE 69
Section 1 Overview Pin Name Pin No.
PAGE 70
Section 1 Overview Pin Name Pin No. Expanded Modes Single-Chip Modes Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Flash Memory Programmer Mode P81 P81 P81/CS2/GA20 NC 76 P82 P82 P82/HIFSD NC 77 P83 P83 P83 NC 78 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC 79 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC 80 P86/IRQ5/SCK1/ SCL1 P86/IRQ5/SCK1/ SCL1 P86/IRQ5/SCK1/ SCL1 NC FP-80A TFP-80C 75 Rev. 4.
PAGE 71
Section 1 Overview Table 1.3 H8S/2134 Group Pin Functions in Each Operating Mode Pin Name Pin No.
PAGE 72
Section 1 Overview Pin Name Pin No.
PAGE 73
Section 1 Overview Pin Name Pin No.
PAGE 74
Section 1 Overview 1.3.3 Pin Functions Table 1.4 summarizes the functions of the H8S/2138 Group and H8S/2134 Group pins. Table 1.4 Pin Functions Pin No. Type Power supply Clock FP-80A TFP-80C I/O Name and Function VCC1, VCC2 8*, 47 Input Power supply: For connection to the power supply. All VCC1 and VCC2* pins should be connected to the system power supply.
PAGE 75
Section 1 Overview Pin No. Type Symbol FP-80A TFP-80C Operating mode control MD1 MD0 4 5 I/O Name and Function Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD1 and MD0 and the operating mode is shown below. These pins should not be changed while the MCU is operating.
PAGE 76
Section 1 Overview Pin No. Type Symbol FP-80A TFP-80C I/O Name and Function Interrupt signals NMI 6 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. IRQ0 to IRQ7 18 to 20, 78 to 80, 27, 28 Input Interrupt request 0 to 7: These pins request a maskable interrupt. FRT counter clock input: Input pin for an external clock signal for the free-running counter (FRC).
PAGE 77
Section 1 Overview Pin No. Type Symbol FP-80A TFP-80C Serial communication interface (SCI0, SCI1, SCI2) TxD0 TxD1 TxD2 11 78 39 Output Transmit data: Data output pins. RxD0 RxD1 RxD2 10 79 40 Input Receive data: Data input pins. SCK0 SCK1 SCK2 9 80 41 Input/ output Serial clock: Clock input/output pins. SCI with IrTxD IrDA (SCI2) IrRxD 39 40 Output IrDA transmit data/receive data: Input and output Input pins for data encoded for IrDA use.
PAGE 78
Section 1 Overview Pin No. FP-80A TFP-80C I/O Name and Function AN7 to AN0 37 to 30 Input Analog input: A/D converter analog input pins. CN0 to CN7 21 to 24, 25 to 28 Input Expansion A/D inputs: Expansion A/D input pins can be connected to the A/D converter, but since they are also used as digital input/output pins, precision will fall. ADTRG 20 Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion.
PAGE 79
Section 1 Overview Pin No. Type Symbol I/O ports P17 to P10 Note: * FP-80A TFP-80C I/O Name and Function 57 to 64 Input/ output Port 1: Eight input/output pins. The data direction of each pin can be selected in the port 1 data direction register (P1DDR). These pins have on-chip MOS input pull-ups, and also have LED drive capability. P27 to P20 48 to 55 Input/ output Port 2: Eight input/output pins. The data direction of each pin can be selected in the port 2 data direction register (P2DDR).
PAGE 80
Section 1 Overview Rev. 4.
PAGE 81
Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features.
PAGE 82
Section 2 CPU • High-speed operation  All frequently-used instructions execute in one or two states  Maximum clock rate: 20 MHz  8/16/32-bit register-register add/subtract: 50 ns  8 × 8-bit register-register multiply: 600 ns  16 ÷ 8-bit register-register divide: 600 ns  16 × 16-bit register-register multiply: 1000 ns  32 ÷ 16-bit register-register divide: 1000 ns • Two CPU operating modes  Normal mode  Advanced mode • Power-down state  Transition to power-down state by SLEEP instruction
PAGE 83
Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit control register, have been added. • Expanded address space  Normal mode supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space.
PAGE 84
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected by the mode pins of the microcontroller.
PAGE 85
Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling.
PAGE 86
Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch (b) Exception Handling Note: * Ignored when returning. Figure 2.
PAGE 87
Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling.
PAGE 88
Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) (a) Subroutine Branch CCR SP PC (24 bits) (b) Exception Handling Figure 2.
PAGE 89
Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2138 Group or H8S/2134 Group H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.6 Memory Map Rev. 4.
PAGE 90
Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers.
PAGE 91
Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
PAGE 92
Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
PAGE 93
Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
PAGE 94
Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
PAGE 95
Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers.
PAGE 96
Section 2 CPU Data Type General Register Word data Rn Word data En Data Format 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) Rev. 4.
PAGE 97
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
PAGE 98
Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.
PAGE 99
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.
PAGE 100
Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
PAGE 101
Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Size* Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2138 Group or H8S/2134 Group. MOVTPE B Cannot be used in the H8S/2138 Group or H8S/2134 Group. POP W/L @SP+ → Rn Pops a general register from the stack. 1 POP.W Rn is identical to MOV.
PAGE 102
Section 2 CPU Type Instruction Size* Function Arithmetic operations ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
PAGE 103
Section 2 CPU Type Instruction Size* Function Arithmetic operations DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
PAGE 104
Section 2 CPU Type Instruction Size* Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
PAGE 105
Section 2 CPU Type Instruction Size* Function Bitmanipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
PAGE 106
Section 2 CPU Type Instruction Size* Function Bitmanipulation instructions BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [¬ ( of )] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
PAGE 107
Section 2 CPU Type Instruction Size* Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
PAGE 108
Section 2 CPU Type Instruction Size* Function System control instructions TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. 1 SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves contents of a general register or memory or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
PAGE 109
Section 2 CPU Type Instruction Size* Function Block data transfer instructions EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; 1 Block transfer instruction. Transfers the number of data bytes specified by R4L or R4 from locations starting at the address indicated by ER5 to locations starting at the address indicated by ER6. After the transfer, the next instruction is executed.
PAGE 110
Section 2 CPU Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.12 Instruction Formats (Examples) 2.6.
PAGE 111
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
PAGE 112
Section 2 CPU Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
PAGE 113
Section 2 CPU Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
PAGE 114
Section 2 CPU If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode.
PAGE 115
Section 2 CPU Table 2.6 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct (Rn) op 2 Effective Address Calculation Effective Address (EA) Operand is general register contents.
PAGE 116
Section 2 CPU No. Addressing Mode and Instruction Format 5 Absolute address Effective Address Calculation Effective Address (EA) @aa:8 31 op abs @aa:16 31 op 0 H'FFFF 24 23 16 15 Sign extension 0 24 23 0 Don’t care abs @aa:24 31 op 87 24 23 Don’t care Don’t care abs @aa:32 op 31 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 24 23 0 Don’t care Operand is immediate data. IMM Program-counter relative @(d:8, PC)/@(d:16, PC) 0 23 PC contents op disp Rev. 4.
PAGE 117
Section 2 CPU No. Addressing Mode and Instruction Format 8 Memory indirect @@aa:8 • Effective Address Calculation Effective Address (EA) Normal mode op abs 31 87 0 abs H'000000 31 24 23 Don’t care 16 15 0 H'00 0 15 Memory contents • Advanced mode op abs 31 87 H'000000 31 0 abs 0 Memory contents 31 24 23 0 Don’t care Rev. 4.
PAGE 118
Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
PAGE 119
Section 2 CPU End of bus request Bus request Program execution state End of bus request SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1.
PAGE 120
Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority.
PAGE 121
Section 2 CPU Figure 2.16 shows the stack after exception handling ends. Normal mode SP Advanced mode CCR CCR* SP CCR PC (24 bits) PC (16 bits) Note: * Ignored when returning. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU.
PAGE 122
Section 2 CPU stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. For details, refer to section 24, Power-Down State. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power control register (LPWRCR) are both cleared to 0.
PAGE 123
Section 2 CPU Bus cycle T1 φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 On-Chip Memory Access Cycle Bus cycle T1 φ Address bus Unchanged AS High RD High WR High Data bus High impedance Figure 2.18 Pin States during On-Chip Memory Access Rev. 4.
PAGE 124
Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
PAGE 125
Section 2 CPU Bus cycle T1 T2 φ Address bus Unchanged AS High RD High WR High Data bus High impedance Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. Rev. 4.
PAGE 126
Section 2 CPU 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.
PAGE 127
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2138 Group and H8S/2134 Group have three operating modes (modes 1 to 3). These modes enable selection of the CPU operating mode and enabling/disabling of on-chip ROM, by setting the mode pins (MD1 and MD0). Table 3.1 lists the MCU operating modes. Table 3.
PAGE 128
Section 3 MCU Operating Modes 3.1.2 Register Configuration The H8S/2138 Group and H8S/2134 Group have a mode control register (MDCR) that indicates the inputs at the mode pins (MD1 and MD0), a system control register (SYSCR) and bus control register (BCR) that control the operation of the MCU, and a serial timer control register (STCR) that controls the operation of the supporting modules. Table 3.2 summarizes these registers. Table 3.
PAGE 129
Section 3 MCU Operating Modes Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1 and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and written. Bit 7 EXPE Description 0 Single chip mode is selected 1 Expanded mode is selected Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
PAGE 130
Section 3 MCU Operating Modes Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode. Bit 6 IOSE Description 0 The AS/IOS pin functions as the address strobe pin (AS) (Low output when accessing an external area) The AS/IOS pin functions as the I/O strobe pin (IOS) (Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)* 1 Note: (Initial value) * In the H8S/2138 F-ZTAT A-mask version, the address range is from H'(FF)F000 to H'(FF)F7FF.
PAGE 131
Section 3 MCU Operating Modes Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled 3.2.
PAGE 132
Section 3 MCU Operating Modes 3.2.4 Serial Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 — IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions), and also selects the TCNT input clock.
PAGE 133
Section 3 MCU Operating Modes Bit 4 IICE Description 0 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used for SCI1 control register access (Initial value) Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used for SCI2 control register access Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used for SCI0 control register access 1 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used for IIC1 data register and
PAGE 134
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 function as a data bus, and part of port 9 carries bus control signals. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses.
PAGE 135
Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 to 3, and 9 vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.
PAGE 136
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 On-chip RAM* On-chip RAM* H'EFFF H'E080 H'EFFF H'EFFF External address space H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O register
PAGE 137
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM H'01FFFF H'020000 On-chip ROM H'01FFFF External address space*2 H'FFE080 H'FFE080 On-chip RAM*1 On-chip RAM H'FFEFFF H'FFEFFF External address space*2 H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FF
PAGE 138
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 H'E080 On-chip RAM* On-chip RAM* H'EFFF H'EFFF H'EFFF External address space H'F800 Reserved area H'FE4F H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F
PAGE 139
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM H'01FFFF H'020000 On-chip ROM H'01FFFF External address space*2 H'FFE080 H'FFE080 On-chip RAM*1 On-chip RAM H'FFEFFF H'FFEFFF External address space*2 H'FFF800 Reserved area H'FFFE4F H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF H'FFFE50 H'FFFEFF
PAGE 140
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 H'E080 On-chip RAM* On-chip RAM* H'EFFF H'EFFF H'EFFF External address space H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O register
PAGE 141
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'017FFF H'017FFF Reserved area H'01FFFF H'020000 Reserved area H'01FFFF External address space*2 H'FFE080 H'FFE080 On-chip RAM*1 On-chip RAM H'FFEFFF H'FFEFFF External address space*2 H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF
PAGE 142
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'DFFF H'DFFF External address space H'E080 H'E880 H'EFFF H'E080 H'E080 Reserved area* Reserved area* On-chip RAM* H'E880 H'EFFF External address space H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'F
PAGE 143
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF Reserved area H'01FFFF H'020000 Reserved area H'01FFFF External address space*2 H'FFE080 H'FFE080 Reserved area*1 H'FFE880 H'FFEFFF On-chip RAM*1 Reserved area H'FFE880 H'FFEFFF On-chip RAM External address space*2 H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'
PAGE 144
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'7FFF H'7FFF Reserved area H'DFFF Reserved area H'DFFF External address space H'E080 H'E880 H'EFFF H'E080 H'E080 Reserved area* Reserved area* On-chip RAM* H'E880 H'EFFF External address space H'FE50 H'FEFF Internal I/O register
PAGE 145
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM H'007FFF H'007FFF Reserved area H'01FFFF H'020000 Reserved area H'01FFFF External address space*2 H'FFE080 H'FFE080 Reserved area*1 H'FFE880 H'FFEFFF On-chip RAM*1 Reserved area H'FFE880 H'FFEFFF On-chip RAM External address space*2 H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H
PAGE 146
Section 3 MCU Operating Modes Rev. 4.
PAGE 147
Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state.
PAGE 148
Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.
PAGE 149
Section 4 Exception Handling Table 4.
PAGE 150
Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. H8S/2138 Group and H8S/2134 Group MCUs can also be reset by overflow of the watchdog timer.
PAGE 151
Section 4 Exception Handling Fetch of Vector Internal first program fetch processing instruction φ RES Internal address bus (1) (3) Internal read signal Internal write signal Internal data bus (1) (2) (3) (4) High (2) (4) Reset exception vector address ((1) = H'0000) Start address (contents of reset exception vector address) Start address ((3) = (2)) First program instruction Figure 4.2 Reset Sequence (Mode 3) Rev. 4.
PAGE 152
Section 4 Exception Handling Vector fetch φ Internal processing Fetch of first program instruction * * * (1) (3) (5) RES Address bus RD High WR (2) D7 to D0 (1) (3) (2) (4) (5) (6) (4) (6) Reset exception vector address ((1) = H'0000, (3) = H'0001) Start address (contents of reset exception vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 1) 4.2.
PAGE 153
Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0) from 17 input pins (NMI, IRQ7 to IRQ0, and KIN7 to KIN0), and internal sources in the on-chip supporting modules. Figure 4.4 shows the interrupt sources and the number of interrupts of each type.
PAGE 154
Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.
PAGE 155
Section 4 Exception Handling 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode) SP CCR PC (24 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode) Rev. 4.
PAGE 156
Section 4 Exception Handling 4.6 Notes on Use of the Stack When accessing word data or longword data, the H8S/2138 Group or H8S/2134 Group chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.
PAGE 157
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features H8S/2138 Group and H8S/2134 Group MCUs control interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
PAGE 158
Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1.
PAGE 159
Section 5 Interrupt Controller 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.
PAGE 160
Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W SYSCR is an 8-bit readable/writable register of which bits 5, 4, and 2 select the interrupt control mode and the detected edge for NMI. Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.
PAGE 161
Section 5 Interrupt Controller 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC) Bit 7 6 5 4 3 2 1 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI and address break. The correspondence between ICR settings and interrupt sources is shown in table 5.3.
PAGE 162
Section 5 Interrupt Controller 5.2.3 IRQ Enable Register (IER) Bit 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode.
PAGE 163
Section 5 Interrupt Controller ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.
PAGE 164
Section 5 Interrupt Controller Bit n IRQnF Description 0 [Clearing conditions] 1 Note: (Initial value) • • Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF • When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1)* When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high* [Setting conditions] • When IRQn input goes low when low-level detec
PAGE 165
Section 5 Interrupt Controller 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) 7 Bit 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix interrupt inputs (pins KIN7 to KIN0) and IRQ6 pin.
PAGE 166
Section 5 Interrupt Controller KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 IRQ6 internal signal KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 IRQ6E IRQ6SC Edge/level selection enable/disable circuit IRQ6 interrupt Figure 5.
PAGE 167
Section 5 Interrupt Controller 5.2.7 Address Break Control Register (ABRKCR) 7 6 5 4 3 2 1 0 CMF — — — — — — BIE Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — — R/W Bit ABRKCR is an 8-bit readable/writable register that performs address break control. ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
PAGE 168
Section 5 Interrupt Controller 5.2.
PAGE 169
Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts. 5.3.1 External Interrupts There are nine external interrupt sources from 17 input pins (15 actual pins): NMI, IRQ7 to IRQ0, and KIN7 to KIN0. KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore the H8S/2138 Group or H8S/2134 Group chip from software standby mode.
PAGE 170
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S Q IRQn interrupt request R IRQn input Clear signal Note: n: 7 to 0 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.4 shows the timing of IRQnF setting. φ IRQn input pin IRQnF Figure 5.4 Timing of IRQnF Setting The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
PAGE 171
Section 5 Interrupt Controller Interrupts KIN7 to KIN0: Interrupts KIN7 to KIN0 are requested by input signals at pins KIN7 to KIN0. When any of pins KIN7 to KIN0 are used as key-sense inputs, the corresponding KMIMR bits should be cleared to 0 to enable those key-sense input interrupts. The remaining unused key-sense input KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN7 to KIN0 correspond to the IRQ6 interrupt.
PAGE 172
Section 5 Interrupt Controller Table 5.
PAGE 173
Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector Address Vector Normal Number Mode Advanced Mode ICR CMIA0 (compare-match A) CMIB0 (compare-match B) OVI0 (overflow) Reserved 8-bit timer channel 0 64 65 66 67 H'0080 H'0082 H'0084 H'0086 H'000100 H'000104 H'000108 H'00010C ICRB3 CMIA1 (compare-match A) CMIB1 (compare-match B) OVI1 (overflow) Reserved 8-bit timer channel 1 68 69 70 71 H'0088 H'008A H'008C H'008E H'000110 H'000114 H'000118 H'00011C ICRB2 CMIAY (
PAGE 174
Section 5 Interrupt Controller 5.4 Address Breaks 5.4.1 Features With the H8S/2138 Group and H8S/2134 Group, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.4.
PAGE 175
Section 5 Interrupt Controller 5.4.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction.
PAGE 176
Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Vector fetch Stack save Internal Instruction operation fetch φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 NOP NOP NOP execution execution execution SP-4 H'0036 Interrupt exception handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP
PAGE 177
Section 5 Interrupt Controller 5.5 Interrupt Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2138 Group and H8S/2134 Group differ depending on the interrupt control mode. NMI and address break interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
PAGE 178
Section 5 Interrupt Controller Figure 5.7 shows a block diagram of the priority decision circuit. I UI ICR Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.
PAGE 179
Section 5 Interrupt Controller Table 5.
PAGE 180
Section 5 Interrupt Controller 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case. 1.
PAGE 181
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI? No No Control level 1 interrupt? Hold pending Yes No No IRQ0? Yes IRQ0? No Yes IRQ1? Yes No IRQ1? Yes IICI1? IICI1? Yes Yes No I = 0? Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 4.
PAGE 182
Section 5 Interrupt Controller 5.5.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. • Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1.
PAGE 183
Section 5 Interrupt Controller Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending.
PAGE 184
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI? No No Control level 1 interrupt? Hold pending Yes IRQ0? Yes No No IRQ0? No Yes IRQ1? No IRQ1? Yes Yes IICI1? IICI1? Yes Yes No I = 0? Yes UI = 0? I = 0? No No Yes Yes Save PC and CCR I ← 1, UI ← 1 Read vector address Branch to interrupt handling routine Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 4.
PAGE 185
Section 5 Interrupt Controller 5.5.4 Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 4.
PAGE 186
Rev. 4.00 Jun 06, 2006 page 130 of 1004 REJ09B0301-0400 Figure 5.11 Interrupt Exception Handling (1) (2) (4) (3) Instruction prefetch Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
PAGE 187
Section 5 Interrupt Controller 5.5.5 Interrupt Response Times The H8S/2138 Group and H8S/2134 Group are capable of fast word access to on-chip memory, and high-speed processing can be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM. Table 5.8 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 5.8 are explained in table 5.9.
PAGE 188
Section 5 Interrupt Controller 5.6 Usage Notes 5.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
PAGE 189
Section 5 Interrupt Controller The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.6.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts, including NMI, are disabled, and the next instruction is always executed.
PAGE 190
Section 5 Interrupt Controller 5.7 DTC Activation by Interrupt 5.7.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller [H8S/2138 Group]. 5.7.2 Block Diagram Figure 5.13 shows a block diagram of the DTC and interrupt controller.
PAGE 191
Section 5 Interrupt Controller 5.7.3 Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
PAGE 192
Section 5 Interrupt Controller Usage Note: SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit. Rev. 4.
PAGE 193
Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The H8S/2138 Group and H8S/2134 Group have an on-chip bus controller (BSC) that allows external address space bus specifications, such as bus width and number of access states, to be set. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below.
PAGE 194
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. External bus control signals Internal control signals Bus controller Bus mode signal WSCR BCR WAIT Internal data bus Wait controller CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev. 4.
PAGE 195
Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.
PAGE 196
Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Control Register (BCR) 7 6 ICIS1 ICIS0 Initial value 1 1 0 1 Read/Write R/W R/W R/W R/W Bit 5 4 3 2 1 0 — IOS1 IOS0 0 1 1 1 R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the extent of the I/O area when the I/O strobe function has been selected for the AS pin.
PAGE 197
Section 6 Bus Controller Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max.
PAGE 198
Section 6 Bus Controller Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): These are reserved bits. Always write 0 when writing to these bits in the A-mask version. Bit 5—Bus Width Control (ABW): Specifies whether the external memory space is 8-bit access space or 16-bit access space. However, a 16-bit access space cannot be specified for these group, and therefore 0 should not be written to this bit.
PAGE 199
Section 6 Bus Controller Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0): These bits select the number of program wait states when external memory space is accessed while the AST bit is set to 1. Bit 1 Bit 0 WC1 WC0 Description 0 0 No program wait states are inserted 1 1 program wait state is inserted in external memory space accesses 0 2 program wait states are inserted in external memory space accesses 1 3 program wait states are inserted in external memory space accesses (Initial value) 1 6.
PAGE 200
Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) Bus Specifications (Basic Bus Interface) Access States Program Wait States ABW AST WMS1 WMS0 WC1 WC0 Bus Width 0 0 — — — — Cannot be used in the H8S/2138 Group or H8S/2134 Group. 1 0 — — — — 8 2 0 1 0 1 — — 8 3 0 —* —* 0 0 3 0 1 Note: 6.3.
PAGE 201
Section 6 Bus Controller 6.3.4 I/O Select Signal In the H8S/2138 Group and H8S/2134 Group, an I/O select signal (IOS) can be output, with the signal output going low when the designated external space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 φ Address bus External address in IOS set range IOS Figure 6.2 IOS Signal Output Timing Enabling or disabling of IOS signal output is controlled by the setting of the IOSE bit in SYSCR.
PAGE 202
Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with the AST bit, and the WMS1, WMS0, WC1, and WC0 bits (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
PAGE 203
Section 6 Bus Controller 16-Bit Access Space (Cannot Be Used in the H8S/2138 Group or H8S/2134 Group): Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses.
PAGE 204
Section 6 Bus Controller Table 6.5 Data Buses Used and Valid Strobes Area 8-bit access space Access Size Read/ Write Address Valid Strobe Upper Data Bus 1 (D15 to D8)* Lower Data Bus 3 (D7 to D0)* Byte Read — RD Valid Port, etc. — 2 HWR* Even RD 16-bit access Byte space (Cannot be used in the H8S/2138 Group or H8S/2134 Group) Word Write Read Odd Port, etc.
PAGE 205
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit 2-State Access Space Rev. 4.
PAGE 206
Section 6 Bus Controller 8-Bit 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. These group have no lower data bus (D7 to D0) pins or LWR pin. In these group, the upper data bus (D15 to D8) pins are designated D7 to D0, and the HWR signal pin is designated WR.
PAGE 207
Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the MCU can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: program wait insertion, pin wait insertion using the WAIT pin, and a combination of the two. Program Wait Mode In program wait mode, the number of TW states specified by bits WC1 and WC0 are always inserted between the T2 and T3 states when external space is accessed.
PAGE 208
Section 6 Bus Controller By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS (IOSE = 0) RD Read Data bus Read data WR Write Data bus Note: Write data indicates the timing of WAIT pin sampling using the φ clock. Figure 6.7 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input disabled. Rev. 4.
PAGE 209
Section 6 Bus Controller 6.5 Burst ROM Interface 6.5.1 Overview With the H8S/2138 Group and H8S/2134 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. External space can be designated as burst ROM space by means of the BRSTRM bit in BCR. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.
PAGE 210
Section 6 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.8 (a) Example of Burst ROM Access Timing (When AST = BRSTS1 = 1) Full access T1 T2 Burst access T1 T1 φ Only lower address changed Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.8 (b) Example of Burst ROM Access Timing (When AST = BRSTS1 = 0) Rev. 4.
PAGE 211
Section 6 Bus Controller 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 6.6 Idle Cycle 6.6.
PAGE 212
Section 6 Bus Controller Bus cycle A T1 T2 Bus cycle A Bus cycle B T3 T1 T2 T1 φ φ Address bus Address bus RD RD WR WR Data bus Data bus Long output floating time T2 Pin States in Idle Cycle Table 6.6 shows pin states in an idle cycle. Pin States in Idle Cycle Pins Pin State A15 to A0, IOS Contents of next bus cycle D7 to D0 High impedance AS High RD High WR High Rev. 4.00 Jun 06, 2006 page 156 of 1004 REJ09B0301-0400 T1 (b) Idle cycle inserted Figure 6.
PAGE 213
Section 6 Bus Controller 6.7 Bus Arbitration 6.7.1 Overview The H8S/2138 Group and H8S/2134 Group have a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and the DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
PAGE 214
Section 6 Bus Controller 6.7.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the DTC.
PAGE 215
Section 7 Data Transfer Controller [H8S/2138 Group] Section 7 Data Transfer Controller [H8S/2138 Group] Provided in the H8S/2138 Group; not provided in the H8S/2134 Group. 7.1 Overview The H8S/2138 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.
PAGE 216
Section 7 Data Transfer Controller [H8S/2138 Group] 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
PAGE 217
Section 7 Data Transfer Controller [H8S/2138 Group] 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.
PAGE 218
Section 7 Data Transfer Controller [H8S/2138 Group] 7.2 Register Descriptions 7.2.1 DTC Mode Register A (MRA) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRA is an 8-bit register that controls the DTC operating mode.
PAGE 219
Section 7 Data Transfer Controller [H8S/2138 Group] Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 MD1 MD0 Description 0 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 — 1 Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
PAGE 220
Section 7 Data Transfer Controller [H8S/2138 Group] 7.2.2 DTC Mode Register B (MRB) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer.
PAGE 221
Section 7 Data Transfer Controller [H8S/2138 Group] 7.2.3 DTC Source Address Register (SAR) 23 Bit Initial value Read/write 22 21 20 19 4 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.
PAGE 222
Section 7 Data Transfer Controller [H8S/2138 Group] 7.2.
PAGE 223
Section 7 Data Transfer Controller [H8S/2138 Group] A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number generated by the interrupt controller in each case. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR.
PAGE 224
Section 7 Data Transfer Controller [H8S/2138 Group] Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is H'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 7.2.
PAGE 225
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3 Operation 7.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
PAGE 226
Section 7 Data Transfer Controller [H8S/2138 Group] The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 7.2 outlines the functions of the DTC. Table 7.
PAGE 227
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software (software activation). An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding bit is set to 1, and to the CPU when the bit is cleared to 0.
PAGE 228
Section 7 Data Transfer Controller [H8S/2138 Group] Source flag cleared Clear control Clear DTCER Clear request On-chip supporting module IRQ interrupt Interrupt request Selection circuit Select DTVECR DTC Interrupt controller CPU Interrupt mask Figure 7.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect.
PAGE 229
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.3 DTC Vector Table Figure 7.4 shows the correspondence between DTC vector addresses and register information. Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + DTVECR[6:0] << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
PAGE 230
Section 7 Data Transfer Controller [H8S/2138 Group] Table 7.
PAGE 231
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (vector address contents). In chain transfer, locate the register information in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF).
PAGE 232
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. Table 7.
PAGE 233
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial address register state specified by the transfer counter and repeat area resumes and transfer is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.
PAGE 234
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is specified as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified in the block area is restored. The other address register is successively incremented or decremented, or left fixed.
PAGE 235
Section 7 Data Transfer Controller [H8S/2138 Group] First block SAR or DAR · · · Block area DAR or SAR Transfer Nth block Figure 7.8 Memory Mapping in Block Transfer Mode Rev. 4.
PAGE 236
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows memory mapping for chain transfer.
PAGE 237
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.9 Operation Timing Figures 7.10 to 7.12 show examples of DTC operation timing. φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.
PAGE 238
Section 7 Data Transfer Controller [H8S/2138 Group] φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 7.12 DTC Operation Timing (Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of states required for each execution phase. Table 7.
PAGE 239
Section 7 Data Transfer Controller [H8S/2138 Group] Table 7.
PAGE 240
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.11 Procedures for Using the DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
PAGE 241
Section 7 Data Transfer Controller [H8S/2138 Group] 7.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
PAGE 242
Section 7 Data Transfer Controller [H8S/2138 Group] Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
PAGE 243
Section 7 Data Transfer Controller [H8S/2138 Group] 7.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
PAGE 244
Section 7 Data Transfer Controller [H8S/2138 Group] Rev. 4.
PAGE 245
Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview The H8S/2138 Group and H8S/2134 Group have eight I/O ports (ports 1 to 6, 8, and 9), and one input-only port (port 7). Tables 8.1 and 8.2 summarize the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, and 6 have an on-chip MOS input pull-up function.
PAGE 246
Section 8 I/O Ports Table 8.
PAGE 247
Section 8 I/O Ports Expanded Modes Port Description Pins Port 4 • 8-bit I/O port P47/PWX1 P46/PWX0 P45/TMRI1/ HIRQ12/CSYNCI P44/TMO1/ HIRQ1/HSYNCO P43/TMCI1/ HIRQ11/HSYNCI P42/TMRI0/SCK2/ SDA1 P41/TMO0/RxD2/ IrRxD P40/TMCI0/TxD2/ IrTxD Port 5 • 3-bit I/O port P52/SCK0/SCL0 P51/RxD0 Mode 1 Mode 2, Mode 3 (EXPE = 1) I/O port also functioning as 14-bit PWM timer output (PWX1, PWX0), 8-bit timer 0 and 1 input/output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection input/output (HSYNCO, CSYNCI,
PAGE 248
Section 8 I/O Ports Expanded Modes Port Description Port 7 • 8-bit input port Pins P77/AN7/DA1 P76/AN6/DA0 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) Input port also functioning as A/D converter analog input (AN7 to AN0) and D/A converter analog output (DA1, DA0) P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 8 • 7-bit I/O port P86/IRQ5/SCK1/ SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 I/O port also functioning as external interrupt input (IRQ5, IRQ4, IRQ3), SCI1 input/o
PAGE 249
Section 8 I/O Ports Table 8.
PAGE 250
Section 8 I/O Ports Expanded Modes Port Description Pins Port 6 • 8-bit I/O port P67/IRQ7/KIN7/ CIN7 P66/IRQ6/FTOB/ KIN6/CIN6 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as external interrupt input (IRQ7, IRQ6), FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB), 8-bit timer Y input (TMIY), key-sense interrupt input (KIN7 to KIN0), and expansion A/D converter input (CIN7 to CIN0) P65/FTID/KIN5/ CIN5 P64/FTIC/KIN4/ CIN4 P63/FTIB/KIN3/
PAGE 251
Section 8 I/O Ports Expanded Modes Port Description Pins Port 9 • 8-bit I/O port P97/WAIT Mode 1 Mode 2, Mode 3 (EXPE = 1) I/O port also functioning as expanded data bus control input (WAIT) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port P96/φ/EXCL When DDR = When DDR = 0 (after reset): input port or EXCL 0: input port or input EXCL input When DDR = 1: φ output When DDR = 1 (after reset): φ output P95/AS/IOS Expanded data bus control output(AS/IOS, WR, RD) P94/WR I/O port P93/RD P92/IRQ0
PAGE 252
Section 8 I/O Ports Port 1 Port 1 pins Pin functions in mode 1 P17/A7/PW7 A7 (Output) P16/A6/PW6 A6 (Output) P15/A5/PW5 A5 (Output) P14/A4/PW4 A4 (Output) P13/A3/PW3 A3 (Output) P12/A2/PW2 A2 (Output) P11/A1/PW1 A1 (Output) P10/A0/PW0 A0 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A7 (Output)/P17 (Input)/PW7 (Output) A6 (Output)/P16 (Input)/PW6 (Output) A5 (Output)/P15 (Input)/PW5 (Output) A4 (Output)/P14 (Input)/PW4 (Output) A3 (Output)/P13 (Input)/PW3 (Output) A2 (Output)/P12 (In
PAGE 253
Section 8 I/O Ports 8.2.2 Register Configuration Table 8.3 shows the port 1 register configuration. Table 8.3 Port 1 Registers Name Abbreviation R/W Initial Value Address* Port 1 data direction register P1DDR W H'00 H'FFB0 Port 1 data register P1DR R/W H'00 H'FFB2 Port 1 MOS pull-up control register P1PCR R/W H'00 H'FFAC Note: * Lower 16 bits of the address.
PAGE 254
Section 8 I/O Ports Port 1 Data Register (P1DR) Bit Initial value R/W 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read, regardless of the actual pin states.
PAGE 255
Section 8 I/O Ports 8.2.3 Pin Functions in Each Mode Mode 1: In mode 1, port 1 pins automatically function as address outputs. The port 1 pin functions are shown in figure 8.2. A7 (Output) A6 (Output) A5 (Output) Port 1 A4 (Output) A3 (Output) A2 (Output) A1 (Output) A0 (Output) Figure 8.
PAGE 256
Section 8 I/O Ports Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 1 pins function as PWM outputs or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input port. The port 1 pin functions are shown in figure 8.4.
PAGE 257
Section 8 I/O Ports 8.2.4 MOS Input Pull-Up Function Port 1 has an on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis. When a P1DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P1PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode.
PAGE 258
Section 8 I/O Ports Port 2 Port 2 pins Pin functions in mode 1 P27/A15/PW15/CBLANK A15 (Output) P26/A14/PW14 A14 (Output) P25/A13/PW13 A13 (Output) P24/A12/PW12 A12 (Output) P23/A11/PW11 A11 (Output) P22/A10/PW10 A10 (Output) P21/A9/PW9 A9 (Output) P20/A8/PW8 A8 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A15 (Output)/P27 (I/O)/PW15 (Output)/CBLANK (Output) A14 (Output)/P26 (I/O)/PW14 (Output) A13 (Output)/P25 (I/O)/PW13 (Output) A12 (Output)/P24 (I/O)/PW12 (Output) A11 (Output)/P2
PAGE 259
Section 8 I/O Ports 8.3.2 Register Configuration Table 8.5 shows the port 2 register configuration. Table 8.5 Port 2 Registers Name Abbreviation R/W Initial Value Address* Port 2 data direction register P2DDR W H'00 H'FFB1 Port 2 data register P2DR R/W H'00 H'FFB3 Port 2 MOS pull-up control register P2PCR R/W H'00 H'FFAD Note: * Lower 16 bits of the address.
PAGE 260
Section 8 I/O Ports • Modes 2 and 3 (EXPE = 0) The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting.
PAGE 261
Section 8 I/O Ports 8.3.3 Pin Functions in Each Mode Mode 1: In mode 1, port 2 pins automatically function as address outputs. The port 2 pin functions are shown in figure 8.6. A15 (Output) A14 (Output) A13 (Output) Port 2 A12 (Output) A11 (Output) A10 (Output) A9 (Output) A8 (Output) Figure 8.
PAGE 262
Section 8 I/O Ports When P2DDR = 1 and PWOERB = 0 When P2DDR = 0 When P2DDR = 1 and PWOERB = 1 A15 (Output)/P27 (Output) P27 (Input)/CBLANK (Output) PW15 (Output)/CBLANK (Output) Port 2 A14 (Output)/P26 (Output) P26 (Input) PW14 (Output) A13 (Output)/P25 (Output) P25 (Input) PW13 (Output) A12 (Output)/P24 (Output) P24 (Input) PW12 (Output) A11 (Output) P23 (Input) PW11 (Output) A10 (Output) P22 (Input) PW10 (Output) A9 (Output) P21 (Input) PW9 (Output) A8 (Output) P20 (Input) PW8 (Out
PAGE 263
Section 8 I/O Ports 8.3.4 MOS Input Pull-Up Function Port 2 has an on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis. When a P2DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P2PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode.
PAGE 264
Section 8 I/O Ports 8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port. Port 3 pins also function as host data bus I/O pins (HDB7 to HDB0) (H8S/2138 Group only), and as data bus I/O pins. Port 3 functions change according to the operating mode. Port 3 has an on-chip MOS input pull-up function that can be controlled by software. Figure 8.9 shows the port 3 pin configuration.
PAGE 265
Section 8 I/O Ports 8.4.2 Register Configuration Table 8.7 shows the port 3 register configuration. Table 8.7 Port 3 Registers Name Abbreviation R/W Initial Value Address* Port 3 data direction register P3DDR W H'00 H'FFB4 Port 3 data register P3DR R/W H'00 H'FFB6 Port 3 MOS pull-up control register P3PCR R/W H'00 H'FFAE Note: * Lower 16 bits of the address.
PAGE 266
Section 8 I/O Ports Port 3 Data Register (P3DR) 7 6 5 4 3 2 1 0 P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30). If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states.
PAGE 267
Section 8 I/O Ports 8.4.3 Pin Functions in Each Mode Modes 1, 2, and 3 (EXPE = 1): In modes 1, 2, and 3 (when EXPE = 1), port 3 pins automatically function as data I/O pins. The port 3 pin functions are shown in figure 8.10. D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) Port 3 D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Figure 8.
PAGE 268
Section 8 I/O Ports 8.4.4 MOS Input Pull-Up Function Port 3 has an on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3 (when EXPE = 0), and can be specified as on or off on a bit-by-bit basis. When a P3DDR bit is cleared to 0 in mode 2 or 3 (when EXPE = 0), setting the corresponding P3PCR bit to 1 turns on the MOS input pull-up for that pin.
PAGE 269
Section 8 I/O Ports 8.5 Port 4 8.5.1 Overview Port 4 is an 8-bit I/O port. Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO) (H8S/2138 Group only), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11) (H8S/2138 Group only), and the IIC1 I/O pin (SDA1) (option in H8S/2138 Group only).
PAGE 270
Section 8 I/O Ports Port 4 Data Direction Register (P4DDR) Bit 7 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned.
PAGE 271
Section 8 I/O Ports Table 8.10 Port 4 Pin Functions Pin Selection Method and Pin Functions P47/PWX1 The pin function is switched as shown below according to the combination of bit OEB in DACR of 14-bit PWM, and bit P47DDR. OEB 0 P47DDR Pin function P46/PWX0 0 1 — P47 input pin P47 output pin PWX1 output pin The pin function is switched as shown below according to the combination of bit OEA in DACR of 14-bit PWM, and bit P46DDR.
PAGE 272
Section 8 I/O Ports Pin Selection Method and Pin Functions P43/TMCI1/ HIRQ11/HSYNCI The pin function is switched as shown below according to the combination of the operating mode and bit P43DDR. P43DDR 0 Operating mode — Not slave mode Slave mode P43 input pin P43 output pin HIRQ11 output pin Pin function 1 TMCI1 input pin, HSYNCI input pin When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1, this pin is used as the TMCI1 input pin.
PAGE 273
Section 8 I/O Ports Pin Selection Method and Pin Functions P41/TMO0/RxD2/ The pin function is switched as shown below according to the combination of IrRxD bits OS3 to OS0 in TCSR of TMR0, bit RE in SCR of SCI2 and bit P41DDR. OS3 to OS0 All 0 RE P41DDR Pin function Not all 0 0 1 0 0 1 — — P41 input pin P41 output pin RxD2/IrRxD input pin TMO0 output pin When this pin is used as the TMO0 output pin, bit RE in SCR of SCI2 must be cleared to 0.
PAGE 274
Section 8 I/O Ports 8.6 Port 5 8.6.1 Overview Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0), and the IIC0 I/O pin (SCL0) (option in H8S/2138 Group only). In the H8S/2138 Group, P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 pin functions are the same in all operating modes. Figure 8.13 shows the port 5 pin configuration.
PAGE 275
Section 8 I/O Ports Port 5 Data Direction Register (P5DDR) 7 6 5 4 3 — — — — — Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — W W W Bit 2 1 0 P52DDR P51DDR P50DDR P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are reserved.
PAGE 276
Section 8 I/O Ports 8.6.3 Pin Functions Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0) and the IIC0 I/O pin (SCL0). The port 5 pin functions are shown in table 8.12. Table 8.12 Port 5 Pin Functions Pin Selection Method and Pin Functions P52/SCK0/SCL0 The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI0, bit C/A in SMR of SCI0, bit ICE in ICCR of IIC0, and bit P52DDR.
PAGE 277
Section 8 I/O Ports 8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port.
PAGE 278
Section 8 I/O Ports 8.7.2 Register Configuration Table 8.13 shows the port 6 register configuration. Table 8.13 Port 6 Registers Name Abbreviation R/W Initial Value 1 Address* Port 6 data direction register P6DDR W H'00 H'FFB9 Port 6 data register P6DR R/W H'00 Port 6 MOS pull-up control register KMPCR R/W H'00 H'FFBB 2 H'FFF2* System control register 2 SYSCR2 R/W H'00 H'FF83 Notes: 1. Lower 16 bits of the address. 2. KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY.
PAGE 279
Section 8 I/O Ports Port 6 Data Register (P6DR) 7 6 5 4 3 2 1 0 P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states.
PAGE 280
Section 8 I/O Ports System Control Register 2 (SYSCR2) [H8S/2138 Group Only] Bit 7 6 KWUL1 KWUL0 5 4 3 2 1 0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W SYSCR2 is an 8-bit readable/writable register that controls port 6 input level selection and the operation of host interface functions. Only bits 7, 6, and 5 are described here. See section 17.2.2, System Control Register 2 (SYSCR2), for information on bits 4 to 0.
PAGE 281
Section 8 I/O Ports 8.7.3 Pin Functions Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO), key-sense interrupt input pins (KIN7 to KIN0), expansion A/D converter input pins (CIN7 to CIN0), and external interrupt input pins (IRQ7, IRQ6).
PAGE 282
Section 8 I/O Ports Pin Selection Method and Pin Functions P64/FTIC/KIN4/ CIN4/CLAMPO The pin function is switched as shown below according to the combination of bit CLOE in TCONRO of the timer connection function and bit P64DDR. CLOE 0 P64DDR Pin function 1 0 1 — P64 input pin P64 output pin CLAMPO output pin FTIC input pin, KIN4 input pin, CIN4 input pin This pin can always be used as the FTIC, KIN4, or CIN4 input pin.
PAGE 283
Section 8 I/O Ports Pin Selection Method and Pin Functions P60/FTCI/TMIX/ KIN0/CIN0/ HFBACKI P60DDR Pin function 0 1 P60 input pin P60 output pin FTCI input pin, HFBACKI input pin, TMIX input pin, KIN0 input pin, CIN0 input pin This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the TMIX, KIN0, CIN0, or HFBACKI input pin. 8.7.
PAGE 284
Section 8 I/O Ports 8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit input port. Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Port 7 functions are the same in all operating modes. Figure 8.15 shows the port 7 pin configuration.
PAGE 285
Section 8 I/O Ports Port 7 Input Data Register (P7PIN) 7 Bit P77PIN 6 5 P76PIN P75PIN 4 3 2 P74PIN P73PIN P72PIN 1 0 P71PIN P70PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins P77 to P70. When a P7PIN read is performed, the pin states are always read. 8.8.3 Pin Functions Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Rev. 4.
PAGE 286
Section 8 I/O Ports 8.9 Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1) (option in H8S/2138 Group only), HIF I/O pins (CS2, GA20, HA0, HIFSD) (H8S/2138 Group only), and external interrupt input pins (IRQ5 to IRQ3). Port 8 pin functions are the same in all operating modes. Figure 8.16 shows the port 8 pin configuration.
PAGE 287
Section 8 I/O Ports Port 8 Data Direction Register (P8DDR) Bit 7 — 6 5 4 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write — W W W W W W W P8DDR is a 7-bit write-only register, the individual bits of which specify input or output for the pins of port 8. Setting a P8DDR bit to 1 makes the corresponding port 8 pin an output pin, while clearing the bit to 0 makes the pin an input pin.
PAGE 288
Section 8 I/O Ports Table 8.18 Port 8 Pin Functions Pin Selection Method and Pin Functions P86/IRQ5/SCK1/ SCL1 The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI1, bit C/A in SMR of SCI1, bit ICE in ICCR of IIC1, and bit P86DDR.
PAGE 289
Section 8 I/O Ports Pin Selection Method and Pin Functions P83 The pin function is switched as shown below according to bit P83DDR. P83DDR Pin function P82/HIFSD 0 1 P83 input pin P83 output pin The pin function is switched as shown below according to the combination of operating mode, bit SDE in SYSCR2 of the HIF, and bit P82DDR.
PAGE 290
Section 8 I/O Ports 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter external trigger input pin (ADTRG), host interface input pins (ECS2, CS1, IOW, IOR) (H8S/2138 Group only), the IIC0 I/O pin (SDA0) (option in H8S/2138 Group only), the subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, WR, WAIT), and the system clock (φ) output pin.
PAGE 291
Section 8 I/O Ports 8.10.2 Register Configuration Table 8.19 summarizes the port 9 registers. Table 8.19 Port 9 Registers Name Abbreviation R/W Initial Value 1 Address* Port 9 data direction register P9DDR W H'40/H'00* H'FFC0 Port 9 data register P9DR R/W H'00 2 H'FFC1 Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode.
PAGE 292
Section 8 I/O Ports • Modes 2 and 3 (EXPE = 0) When the corresponding P9DDR bits are set to 1, pin P96 functions as the φ output pin and pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the corresponding pins become input ports. Port 9 Data Register (P9DR) Bit 7 6 5 4 3 2 1 0 P97DR P94DR P93DR P92DR P91DR P90DR 0 P96DR —* P95DR Initial value 0 0 0 0 0 0 Read/Write R/W R R/W R/W R/W R/W R/W R/W Note: * Determined by the state of pin P96.
PAGE 293
Section 8 I/O Ports Table 8.20 Port 9 Pin Functions Pin Selection Method and Pin Functions P97/WAIT/SDA0 The pin function is switched as shown below according to the combination of operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR.
PAGE 294
Section 8 I/O Ports Pin Selection Method and Pin Functions P94/WR/IOW The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P94DDR. Operating mode — P94DDR — 0 1 — WR output pin P94 input pin P94 output pin IOW input pin 0 1 The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P93DDR.
PAGE 295
Section 8 I/O Ports Pin Selection Method and Pin Functions P90/IRQ2/ ADTRG/ECS2 The pin function is switched as shown below according to the combination of operating mode, bits HI12E and CS2E in SYSCR2, bit FGA20E in HICR, and bit P90DDR.
PAGE 296
Section 8 I/O Ports Rev. 4.
PAGE 297
Section 9 8-Bit PWM Timers [H8S/2138 Group] Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.1 Overview The H8/2138 Group has an on-chip pulse width modulation (PWM) timer module with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division.
PAGE 298
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the PWM timer module.
PAGE 299
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.1.3 Pin Configuration Table 9.1 shows the PWM output pin. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWM output pin 0 to 15 PW0 to PW15 Output PWM timer pulse output 0 to 15 9.1.4 Register Configuration Table 9.2 lists the registers of the PWM timer module. Table 9.
PAGE 300
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.2 Register Descriptions 9.2.1 PWM Register Select (PWSL) Bit 7 6 PWCKE PWCKS 5 4 3 2 1 0 — — RS3 RS2 RS1 RS0 Initial value 0 0 1 0 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the PWM data register. PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode.
PAGE 301
Section 9 8-Bit PWM Timers [H8S/2138 Group] Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz Table 9.3 Internal Clock Frequency Resolution PWM Conversion Period Carrier Frequency φ 50 ns 12.8 µs 1250 kHz φ/2 100 ns 25.6 µs 625 kHz φ/4 200 ns 51.2 µs 312.5 kHz φ/8 400 ns 102.4 µs 156.3 kHz φ/16 800 ns 204.8 µs 78.1 kHz Bit 5—Reserved: This bit is always read as 1 and cannot be modified. Bit 4—Reserved: This bit is always read as 0 and cannot be modified.
PAGE 302
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.2.2 PWM Data Registers (PWDR0 to PWDR15) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period.
PAGE 303
Section 9 8-Bit PWM Timers [H8S/2138 Group] PWDPR is initialized to H'00 by a reset and in hardware standby mode. OS Description 0 PWM direct output (PWDR value corresponds to high width of output) 1 PWM inverted output (PWDR value corresponds to low width of output) 9.2.
PAGE 304
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.2.5 Peripheral Clock Select Register (PCSR) Bit 7 6 5 4 3 — — — — — 2 1 PWCKB PWCKA 0 — Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — — R/W R/W — PCSR is an 8-bit readable/writable register that selects the PWM timer input clock. PCSR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0.
PAGE 305
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.2.7 Port 2 Data Direction Register (P2DDR) Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port J on a bit-by-bit basis. Port 2 pins are multiplexed with pins PW8 to PW15.
PAGE 306
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
PAGE 307
Section 9 8-Bit PWM Timers [H8S/2138 Group] 9.3 Operation 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, as shown in table 9.4. Table 9.4 Upper 4 Bits 0000 Duty Cycle of Basic Pulse Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0001 0010 0011 0100 0101 0110 0111 .. . 1000 1001 1010 1011 1100 1101 1110 1111 Rev. 4.
PAGE 308
Section 9 8-Bit PWM Timers [H8S/2138 Group] The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the resolution, added before the rising edge of a basic pulse. When the upper 4 bits of PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 Position of Pulses Added to Basic Pulses Lower 4 Bits Basic Pulse No.
PAGE 309
Section 10 14-Bit PWM D/A Section 10 14-Bit PWM D/A 10.1 Overview The H8S/2138 Group and H8S/2134 Group have an on-chip 14-bit pulse-width modulator (PWM) with two output channels. Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Both channels share the same counter (DACNT) and control register (DACR). 10.1.1 Features The features of the 14-bit PWM D/A are listed below. • The pulse is subdivided into multiple base cycles to reduce ripple.
PAGE 310
Section 10 14-Bit PWM D/A 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the PWM D/A module.
PAGE 311
Section 10 14-Bit PWM D/A 10.1.3 Pin Configuration Table 10.1 lists the pins used by the PWM D/A module. Table 10.1 Input and Output Pins Name Abbr. I/O Function PWM output pin 0 PWX0 Output PWM output, channel A PWM output pin 1 PWX1 Output PWM output, channel B 10.1.4 Register Configuration Table 10.2 lists the registers of the PWM D/A module. Table 10.
PAGE 312
Section 10 14-Bit PWM D/A 10.2 Register Descriptions 10.2.1 PWM D/A Counter (DACNT) DACNTH DACNTL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIT (Counter) 7 6 5 4 3 2 1 0 8 9 10 11 12 13 — — — REGS Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 — R/W DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse.
PAGE 313
Section 10 14-Bit PWM D/A 10.2.
PAGE 314
Section 10 14-Bit PWM D/A Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an analog value is set in the upper 14 bits of the PWM D/A data register. In each base cycle, the DACNT value is continually compared with these upper 14 bits to determine the duty cycle of the output waveform, and to decide whether to output a fineadjustment pulse equal in width to the resolution.
PAGE 315
Section 10 14-Bit PWM D/A 10.2.3 PWM D/A Control Register (DACR) Bit 7 6 5 4 3 2 1 0 TEST PWME — — OEB OEA OS CKS Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and selects the output phase and operating speed. DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode.
PAGE 316
Section 10 14-Bit PWM D/A Bit 2—Output Enable A (OEA): Enables or disables output on PWM D/A channel A. Bit 2 OEA Description 0 PWM (D/A) channel A output (at the PWX0 pin) is disabled 1 PWM (D/A) channel A output (at the PWX0 pin) is enabled (Initial value) Bit 1—Output Select (OS): Selects the phase of the PWM D/A output. Bit 1 OS Description 0 Direct PWM output 1 Inverted PWM output (Initial value) Bit 0—Clock Select (CKS): Selects the PWM D/A resolution.
PAGE 317
Section 10 14-Bit PWM D/A 10.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
PAGE 318
Section 10 14-Bit PWM D/A 10.3 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written and read as follows (taking the example of the CPU interface). • Write When the upper byte is written, the upper-byte write data is stored in TEMP.
PAGE 319
Section 10 14-Bit PWM D/A Table 10.3 Read and Write Access Methods for 16-Bit Registers Read Write Register Name Word Byte Word DADRA and DADRB Yes Yes Yes DACNT Yes × Yes Byte × × Notes: Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). ×: This type of access may give incorrect results.
PAGE 320
Section 10 14-Bit PWM D/A Upper-Byte Read CPU (H'AA) Upper byte Module data bus Bus interface TEMP (H'57) DACNTH (H'AA) DACNTL (H'57) Lower-Byte Read CPU (H'57) Lower byte Module data bus Bus interface TEMP (H'57) DACNTH ( ) DACNTL ( ) Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT) Rev. 4.
PAGE 321
Section 10 14-Bit PWM D/A 10.4 Operation A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS = 0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figure 10.4 shows the types of waveform output available.
PAGE 322
Section 10 14-Bit PWM D/A Table 10.4 Settings and Operation (Examples when φ = 10 MHz) Base Conversion Resolution CKS CFS Cycle Cycle T (µs) (µs) (µs) 0 0.1 0 6.4 1638.4 Fixed DADR Bits TL (if OS = 0) TH (if OS = 1) 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) × T (DADR = H'0401 to H'FFFD) 1 25.6 1638.4 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) × T (DADR = H'0103 to H'FFFF) 1 0.2 0 12.8 3276.8 1. Always low (or high) (DADR = H'0001 to H'03FD) 2.
PAGE 323
Section 10 14-Bit PWM D/A 1. OS = 0 (DADR corresponds to TL) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL Figure 10.4 (1) Output Waveform b.
PAGE 324
Section 10 14-Bit PWM D/A 2. OS = 1 (DADR corresponds to TH) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tH255 tf256 tH256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH Figure 10.4 (3) Output Waveform b. CFS = 1 [base cycle = resolution (T) × 256] 1 conversion cycle tf1 tH1 tf2 tH2 tf63 tH3 tH63 tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256 tH1 + tH2 + tH3 + · · · + tH63 + tH64 = TH Figure 10.
PAGE 325
Section 11 16-Bit Free-Running Timer Section 11 16-Bit Free-Running Timer 11.1 Overview The H8S/2138 Group and H8S/2134 Group have a single-channel on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 11.1.1 Features The features of the free-running timer module are listed below.
PAGE 326
Section 11 16-Bit Free-Running Timer 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the free-running timer.
PAGE 327
Section 11 16-Bit Free-Running Timer 11.1.3 Input and Output Pins Table 11.1 lists the input and output pins of the free-running timer module. Table 11.
PAGE 328
Section 11 16-Bit Free-Running Timer 11.1.4 Register Configuration Table 11.2 lists the registers of the free-running timer module. Table 11.
PAGE 329
Section 11 16-Bit Free-Running Timer 11.2 Register Descriptions 11.2.1 Free-Running Counter (FRC) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by bits CKS1 and CKS0 in TCR.
PAGE 330
Section 11 16-Bit Free-Running Timer 11.2.3 Input Capture Registers A to D (ICRA to ICRD) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R There are four input capture registers, A to D, each of which is a 16-bit read-only register.
PAGE 331
Section 11 16-Bit Free-Running Timer Table 11.3 Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Description 0 0 Captured on falling edge of input capture A (FTIA) 1 Captured on both rising and falling edges of input capture A (FTIA) 1 (Initial value) 0 1 Captured on rising edge of input capture A (FTIA) To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5φ).
PAGE 332
Section 11 16-Bit Free-Running Timer 11.2.5 Output Compare Register DM (OCRDM) Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
PAGE 333
Section 11 16-Bit Free-Running Timer Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
PAGE 334
Section 11 16-Bit Free-Running Timer Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
PAGE 335
Section 11 16-Bit Free-Running Timer Timing is described in section 11.3, Operation. Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
PAGE 336
Section 11 16-Bit Free-Running Timer Bit 5 ICFC Description 0 [Clearing condition] (Initial value) Read ICFC when ICFC = 1, then write 0 in ICFC 1 [Setting condition] When an input capture signal is received Bit 4—Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal.
PAGE 337
Section 11 16-Bit Free-Running Timer Bit 2—Output Compare Flag B (OCFB): This status flag indicates that the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
PAGE 338
Section 11 16-Bit Free-Running Timer 11.2.8 Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. TCR is initialized to H'00 by a reset and in hardware standby mode.
PAGE 339
Section 11 16-Bit Free-Running Timer Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D signal (FTID). Bit 4 IEDGD Description 0 Capture on the falling edge of FTID 1 Capture on the rising edge of FTID (Initial value) Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for ICRA.
PAGE 340
Section 11 16-Bit Free-Running Timer 11.2.
PAGE 341
Section 11 16-Bit Free-Running Timer Bit 5 ICRS Description 0 The ICRA, ICRB, and ICRC registers are selected 1 The OCRAR, OCRAF, and OCRDM registers are selected (Initial value) Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. This bit does not affect the operation of OCRA or OCRB.
PAGE 342
Section 11 16-Bit Free-Running Timer Bit 1 OLVLA Description 0 0 output at compare-match A 1 1 output at compare-match A (Initial value) Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in response to compare-match B (signal indicating a match between the FRC and OCRB values). Bit 0 OLVLB Description 0 0 output at compare-match B 1 1 output at compare-match B (Initial value) 11.2.
PAGE 343
Section 11 16-Bit Free-Running Timer 11.3 Operation 11.3.1 FRC Increment Timing FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Any of three internal clocks (φ/2, φ/8, or φ/32) created by division of the system clock (φ) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR. Figure 11.3 shows the increment timing. φ Internal clock FRC input clock FRC N–1 N N+1 Figure 11.
PAGE 344
Section 11 16-Bit Free-Running Timer φ External clock input pin FRC input clock FRC N N+1 Figure 11.4 Increment Timing with External Clock Source 11.3.2 Output Compare Output Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A.
PAGE 345
Section 11 16-Bit Free-Running Timer 11.3.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation. φ Compare-match A signal FRC N H'0000 Figure 11.6 Clearing of FRC by Compare-Match A 11.3.4 Input Capture Input Timing Input Capture Input Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin, as selected by the corresponding IEDGx (x = A to D) bit in TCR. Figure 11.
PAGE 346
Section 11 16-Bit Free-Running Timer ICRA/B/C/D read cycle T1 T2 φ Input capture input pin Input capture signal Figure 11.8 Input Capture Signal Timing (Input Capture Input When ICRA/B/C/D Is Read) Buffered Input Capture Input Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 11.
PAGE 347
Section 11 16-Bit Free-Running Timer When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however.
PAGE 348
Section 11 16-Bit Free-Running Timer 11.3.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure 11.11 shows the timing of this operation. φ Input capture signal ICFA to ICFD N FRC ICRA to ICRD N Figure 11.11 Setting of Input Capture Flag (ICFA to ICFD) Rev. 4.
PAGE 349
Section 11 16-Bit Free-Running Timer 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 11.
PAGE 350
Section 11 16-Bit Free-Running Timer 11.3.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of this operation. φ FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Setting of Overflow Flag (OVF) 11.3.
PAGE 351
Section 11 16-Bit Free-Running Timer 11.3.9 ICRD and OCRDM Mask Signal Generation When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture function is generated. The mask signal is set by the input capture signal. The mask signal setting timing is shown in figure 11.15. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match.
PAGE 352
Section 11 16-Bit Free-Running Timer 11.4 Interrupts The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.4 lists information about these interrupts. Table 11.
PAGE 353
Section 11 16-Bit Free-Running Timer 11.5 Sample Application In the example below, the free-running timer is used to generate pulse outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: • The CCLRA bit in TCSR is set to 1. • Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB). FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.17 Pulse Output (Example) Rev. 4.
PAGE 354
Section 11 16-Bit Free-Running Timer 11.6 Usage Notes Application programmers should note that the following types of contention can occur in the freerunning timer. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.18 shows this type of contention.
PAGE 355
Section 11 16-Bit Free-Running Timer Contention between FRC Write and Increment: If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.19 shows this type of contention. FRC write cycle T1 T2 φ Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.19 FRC Write-Increment Contention Rev. 4.
PAGE 356
Section 11 16-Bit Free-Running Timer Contention between OCR Write and Compare-Match: If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is inhibited. Figure 11.20 shows this type of contention. If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is inhibited.
PAGE 357
Section 11 16-Bit Free-Running Timer φ Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Compare-match signal Old Data New Data Inhibited FRC N OCRA N N+1 The compare-match signal is inhibited and automatic addition does not occur. Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) Rev. 4.
PAGE 358
Section 11 16-Bit Free-Running Timer Switching of Internal Clock and FRC Operation: When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 11.5. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (φ).
PAGE 359
Section 11 16-Bit Free-Running Timer No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low FRC Operation Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. Rev. 4.
PAGE 360
Section 11 16-Bit Free-Running Timer Rev. 4.
PAGE 361
Section 12 8-Bit Timers Section 12 8-Bit Timers 12.1 Overview The H8S/2138 Group and H8S/2134 Group include an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect comparematches. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of a rectangular-wave output with an arbitrary duty cycle.
PAGE 362
Section 12 8-Bit Timers • Multiple interrupt sources for each channel  TMR0, TMR1, TMRY: Two compare-match interrupts and one overflow interrupt can be requested independently.  TMRX: One input capture source is available. 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1). TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input capture function. For details, see section 13, Timer Connection [H8S/2138 Group].
PAGE 363
Section 12 8-Bit Timers 12.1.3 Pin Configuration Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.
PAGE 364
Section 12 8-Bit Timers 12.1.4 Register Configuration Table 12.2 summarizes the registers of the 8-bit timer module. Table 12.
PAGE 365
Section 12 8-Bit Timers Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access. (Access is not divided into two 8-bit accesses.) In the H8S/2138 Group, certain of the channel X and channel Y registers are assigned to the same address. The TMRX/Y bit in TCONRS determines which register is accessed. 12.2 Register Descriptions 12.2.
PAGE 366
Section 12 8-Bit Timers 12.2.2 Time Constant Register A (TCORA) TCORA0 TCORA1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORAX, TCORAY Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORA is an 8-bit readable/writable register.
PAGE 367
Section 12 8-Bit Timers 12.2.3 Time Constant Register B (TCORB) TCORB0 TCORB1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORBX, TCORBY Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORB is an 8-bit readable/writable register.
PAGE 368
Section 12 8-Bit Timers 12.2.4 Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the clock source and the time at which TCNT is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in hardware standby mode. For details of the timing, see section 12.3, Operation.
PAGE 369
Section 12 8-Bit Timers Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value.
PAGE 370
Section 12 8-Bit Timers TCR Bit 2 Bit 1 STCR Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 0 — — Clock input disabled 0 0 1 — 0 φ/8 internal clock source, counted on the falling edge 0 0 1 — 1 φ/2 internal clock source, counted on the falling edge 0 1 0 — 0 φ/64 internal clock source, counted on the falling edge 0 1 0 — 1 φ/32 internal clock source, counted on the falling edge 0 1 1 — 0 φ/1024 internal clock source, counted on the falling e
PAGE 371
Section 12 8-Bit Timers 12.2.
PAGE 372
Section 12 8-Bit Timers Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB Description 0 [Clearing conditions] 1 • Read CMFB when CMFB = 1, then write 0 in CMFB • When the DTC is activated by a CMIB interrupt (Initial value) [Setting condition] When TCNT = TCORB Bit 6—Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match.
PAGE 373
Section 12 8-Bit Timers TCSR0 Bit 4—A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests by compare-match A. Bit 4 ADTE Description 0 A/D converter start requests by compare-match A are disabled 1 A/D converter start requests by compare-match A are enabled (Initial value) TCSR1 Bit 4—Reserved: This bit cannot be modified and is always read as 1.
PAGE 374
Section 12 8-Bit Timers Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare-match of TCOR and TCNT. OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the effect of compare-match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: trigger output > 1 output > 0 output.
PAGE 375
Section 12 8-Bit Timers 12.2.6 Serial Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 — IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and also selects the TCNT input clock.
PAGE 376
Section 12 8-Bit Timers 12.2.7 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
PAGE 377
Section 12 8-Bit Timers Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2138 Group, some of the TMRX registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed. In the H8S/2134 Group, there is no control of TMRY register access by this bit.
PAGE 378
Section 12 8-Bit Timers 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function] Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORC is an 8-bit readable/writable register. The sum of the contents of TCORC and TICR is continually compared with the value in TCNT. When a match is detected, a compare-match C signal is generated.
PAGE 379
Section 12 8-Bit Timers 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] Bit 7 6 5 4 3 2 1 0 — — — — — — — IS Initial value 1 1 1 1 1 1 1 0 Read/Write — — — — — — — R/W TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. TISR is initialized to H'FE by a reset and in hardware standby mode. Bits 7 to 1—Reserved: Do not write 0 to these bits.
PAGE 380
Section 12 8-Bit Timers 12.2.13 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
PAGE 381
Section 12 8-Bit Timers 12.3 Operation 12.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: An internal clock created by dividing the system clock (φ) can be selected by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. φ Internal clock TCNT input clock TCNT N–1 N N+1 Figure 12.
PAGE 382
Section 12 8-Bit Timers φ External clock input pin TCNT input clock TCNT N–1 N N+1 Figure 12.3 Count Timing for External Clock Input 12.3.2 Compare-Match Timing Setting of Compare-Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated.
PAGE 383
Section 12 8-Bit Timers Timer Output Timing: When compare-match A or B occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare-match A. φ Compare-match A signal Timer output pin Figure 12.
PAGE 384
Section 12 8-Bit Timers 12.3.3 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.7 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.7 Timing of Clearing by External Reset Input 12.3.
PAGE 385
Section 12 8-Bit Timers 12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (comparematch count mode). In this case, the timer operates as described below.
PAGE 386
Section 12 8-Bit Timers 12.3.6 Input Capture Operation TMRX has input capture registers of TICR,TICRR, and TICRF. Narrow pulse width can be measured with TICRR and TICRF, using one capture operation controlled by the ICST bit in the TCONRI register of the timer connection. When TMRIX detects a rising and falling edge successively after the ICST bit has been set to 1, the values of TCNT at that time are transferred to TICRR and TICRF and ICST bit is cleared to 0.
PAGE 387
Section 12 8-Bit Timers T1 TICRR, TICRF read cycle T2 φ TMRIX Input capture signal Figure 12.10 Timing of Input Capture Signal (When Input Capture Input Signal Enters while TICRR and TICRF Are Being Read) (2) Input capture signal input selection Input capture input signal (TMRIX) in TMRX is switched by setting bits in the TCONRI register. Figure 12.11 and table 12.3 show the input capture signal selections. See section 13.2.1, Timer Connection Register I (TCONRI), for details.
PAGE 388
Section 12 8-Bit Timers Table 12.3 Input Capture Signal Selection TCONRI Bit 4 Bit 7 Bit 6 Bit 3 Bit 1 ICST SIMOD1 SIMOD0 HFINV HIINV Description 0 — — — — Input capture function not used 1 0 0 0 — TMIX pin input signal 1 — Inverted signal of TMIX pin input — 0 TMRI1 pin input signal — 1 Inverted signal of TMRI1 pin input — 0 TMCI1 pin input signal — 1 Inverted signal of TMCI1 pin input 1 1 1 Rev. 4.
PAGE 389
Section 12 8-Bit Timers 12.4 Interrupt Sources The TMR0, TMR1, and TMRY 8-bit timers can generate three types of interrupt: compare-match A and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX interrupt. An interrupt is requested when the corresponding interrupt enable bit is set in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. It is also possible to activate the DTC by means of CMIA and CMIB interrupts from TMR0, TMR1, and TMRY.
PAGE 390
Section 12 8-Bit Timers 12.5 8-Bit Timer Application Example In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.12. The control bits are set as follows: • In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared by a TCORA compare-match. • In TCSR, bits OS3 to OS0 are set to B'0110, causing 1 output at a TCORA compare-match and 0 output at a TCORB compare-match.
PAGE 391
Section 12 8-Bit Timers 12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows this operation.
PAGE 392
Section 12 8-Bit Timers 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.14 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.14 Contention between TCNT Write and Increment Rev. 4.
PAGE 393
Section 12 8-Bit Timers 12.6.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 12.15 shows this operation. With TMRX, an ICR input capture contends with a compare-match in the same way as with a write to TCORC. In this case, the input capture has priority and the compare-match signal is inhibited.
PAGE 394
Section 12 8-Bit Timers 12.6.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.7. Table 12.7 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.6.
PAGE 395
Section 12 8-Bit Timers Table 12.8 Switching of Internal Clock and TCNT Operation No. 1 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from low 1 to low* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 CKS bit rewrite 2 Switching from low 2 to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Rev. 4.
PAGE 396
Section 12 8-Bit Timers No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high 3 to low* Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high.
PAGE 397
Section 13 Timer Connection [H8S/2138 Group] Sectio 13 Timer Connection [H8S/2138 Group] Provided in the H8S/2138 Group; not provided in the H8S/2134 Group. 13.1 Overview The H8S/2138 Group allows interconnection between a combination of input signals, the input/output of the single free-running timer (FRT) channel and the three 8-bit timer channels (TMR1, TMRX, and TMRY). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output.
PAGE 398
Rev. 4.00 Jun 06, 2006 page 342 of 1004 REJ09B0301-0400 Figure 13.
PAGE 399
Section 13 Timer Connection [H8S/2138 Group] 13.1.3 Input and Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.
PAGE 400
Section 13 Timer Connection [H8S/2138 Group] 13.1.4 Register Configuration Table 13.2 lists the timer connection registers. Timer connection registers can only be accessed when the HIE bit in SYSCR is 0. Table 13.
PAGE 401
Section 13 Timer Connection [H8S/2138 Group] Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits select the signal source of the IHI and IVI signals.
PAGE 402
Section 13 Timer Connection [H8S/2138 Group] Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV): These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the vertical synchronization signal (VSYNCI).
PAGE 403
Section 13 Timer Connection [H8S/2138 Group] 13.2.2 Timer Connection Register O (TCONRO) Bit 7 6 5 4 3 2 HOE VOE CLOE CBOE HOINV VOINV 1 0 CLOINV CBOINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion, etc. TCONRO is initialized to H'00 by a reset and in hardware standby mode.
PAGE 404
Section 13 Timer Connection [H8S/2138 Group] Bit 5 CLOE Description 0 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin (Initial value) 1 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin Bit 4 CBOE Description 0 The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin 1 In mode 1 (expanded mode with on-chip ROM disabled): The P27/A15/PW15/CBLANK pin functions as the A15 pin (Initial value) In modes 2 and 3 (modes with on-chip ROM enabled): The P27/A15/P
PAGE 405
Section 13 Timer Connection [H8S/2138 Group] Bit 0 CBOINV Description 0 The CBLANK signal is used directly as the CBLANK output 1 The CBLANK signal is inverted before use as the CBLANK output 13.2.
PAGE 406
Section 13 Timer Connection [H8S/2138 Group] Bits 5 and 4—Horizontal Synchronization Output Mode Select 1 and 0 (HOMOD1, HOMOD0): These bits select the signal source and generation method for the IHO signal.
PAGE 407
Section 13 Timer Connection [H8S/2138 Group] Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits select the signal source for the CLO signal (clamp waveform). Bit 6 Bit 1 Bit 0 ISGENE CLMOD1 CLMOD2 Description 0 0 0 The CL1 signal is selected 1 The CL2 signal is selected 0 The CL3 signal is selected 1 (Initial value) 1 1 0 0 The CL4 signal is selected 1 1 0 1 13.2.
PAGE 408
Section 13 Timer Connection [H8S/2138 Group] Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin. Bit 7 VEDG Description 0 [Clearing condition] (Initial value) When 0 is written in VEDG after reading VEDG = 1 1 [Setting condition] When a rising edge is detected on the VSYNCI pin Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin.
PAGE 409
Section 13 Timer Connection [H8S/2138 Group] Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin. Bit 3 VFEDG Description 0 [Clearing condition] (Initial value) When 0 is written in VFEDG after reading VFEDG = 1 1 [Setting condition] When a rising edge is detected on the VFBACKI pin Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH modification condition.
PAGE 410
Section 13 Timer Connection [H8S/2138 Group] Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. Bit 0 IVI Description 0 The IVI signal is low 1 The IVI signal is high 13.2.
PAGE 411
Section 13 Timer Connection [H8S/2138 Group] MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop mode. MSTPCRH Bit 4 MSTP12 Description 0 8-bit timer channel 0 and 1 module stop mode is cleared 1 8-bit timer channel 0 and 1 module stop mode is set (Initial value) MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer connection module stop mode.
PAGE 412
Section 13 Timer Connection [H8S/2138 Group] Table 13.3 Examples of TCR Settings Bit(s) Abbreviation Contents Description 7 CMIEB 0 6 CMIEA 0 Interrupts due to compare-match and overflow are disabled 5 OVIE 0 4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (IHI signal) 2 to 0 CKS2 to CKS0 001 Incremented on internal clock: φ Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings φ:10 MHz φ: 12 MHz φ: 16 MHz φ: 20 MHz H'07 0.8 µs 0.
PAGE 413
Section 13 Timer Connection [H8S/2138 Group] 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMRX can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4 signal can be generated using TMRY.
PAGE 414
Section 13 Timer Connection [H8S/2138 Group] IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) IHI signal CL3 signal TCNT TICR+TCORC TICR Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform.
PAGE 415
Section 13 Timer Connection [H8S/2138 Group] Table 13.
PAGE 416
Section 13 Timer Connection [H8S/2138 Group] IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.3.4 IHI Signal and 2fH Modification By using the timer connection FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated.
PAGE 417
Section 13 Timer Connection [H8S/2138 Group] Table 13.
PAGE 418
Section 13 Timer Connection [H8S/2138 Group] 13.3.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection TMR1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal.
PAGE 419
Section 13 Timer Connection [H8S/2138 Group] Table 13.
PAGE 420
Section 13 Timer Connection [H8S/2138 Group] 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection FRT and TMRY, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant.
PAGE 421
Section 13 Timer Connection [H8S/2138 Group] Table 13.
PAGE 422
Section 13 Timer Connection [H8S/2138 Group] IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR OCRA FRC 6 system clocks 6 system clocks 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart Rev. 4.
PAGE 423
Section 13 Timer Connection [H8S/2138 Group] 13.3.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9. Table 13.
PAGE 424
Section 13 Timer Connection [H8S/2138 Group] 13.3.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10. Table 13.
PAGE 425
Section 13 Timer Connection [H8S/2138 Group] Mode IVI Signal IVO Signal Meaning of IVO Signal Separate mode VSYNCI input IVI signal (without fall modification or IHI synchronization) VSYNCI input (vertical synchronization signal) is output directly IVI signal (without fall modification, with IHI synchronization) Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) IVI signal (with fall modification, without IHI sync
PAGE 426
Section 13 Timer Connection [H8S/2138 Group] Rev. 4.
PAGE 427
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) 14.1 Overview The H8S/2138 Group and H8S/2134 Group have an on-chip watchdog timer with two channels (WDT0, WDT1) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal.
PAGE 428
Section 14 Watchdog Timer (WDT) 14.1.2 Block Diagram Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1. Internal NMI interrupt request signal*2 Interrupt control Overflow Clock Clock select Reset control Internal reset signal*1 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock source TCNT TCSR Module bus Bus interface WDT Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1.
PAGE 429
Section 14 Watchdog Timer (WDT) Internal NMI (interrupt request signal)*2 Interrupt control Overflow Clock φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock select Reset control Internal reset signal*1 Internal clock source TCNT φSUB/2 φSUB/4 φSUB/8 φSUB/16 φSUB/32 φSUB/64 φSUB/128 φSUB/256 TCSR Bus interface Module bus Internal bus WOVI (interrupt request signal) WDT Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1.
PAGE 430
Section 14 Watchdog Timer (WDT) 14.1.3 Pin Configuration Table 14.1 describes the WDT input pin. Table 14.1 WDT Pin Name Symbol I/O Function External subclock input pin EXCL Input WDT1 prescaler counter input clock 14.1.4 Register Configuration The WDT has four registers, as summarized in table 14.2. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 14.
PAGE 431
Section 14 Watchdog Timer (WDT) 14.2 Register Descriptions 14.2.1 Timer Counter (TCNT) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR.
PAGE 432
Section 14 Watchdog Timer (WDT) 14.2.2 Timer Control/Status Register (TCSR) • TCSR0 Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME RSTS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag.
PAGE 433
Section 14 Watchdog Timer (WDT) Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF Description 0 [Clearing conditions] 1 (Initial value) • Write 0 in the TME bit • Read TCSR when OVF = 1*, then write 0 in OVFA [Setting condition] When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
PAGE 434
Section 14 Watchdog Timer (WDT) TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For details, see the description of the CKS2 to CKS0 bits below. TCSR1 Bit 4 PSS Description 0 TCNT counts φ-based prescaler (PSM) divided clock pulses 1 TCNT counts φSUB-based prescaler (PSS) divided clock pulses (Initial value) Bit 3—Reset or NMI (RST/NMI NMI): NMI Specifies whether an internal reset or NMI interrupt is requested on TCNT overflow in watchdog timer mode.
PAGE 435
Section 14 Watchdog Timer (WDT) • WDT1 input clock selection Bit 4 Bit 2 Bit 1 Bit 0 PSS CKS2 CKS1 CKS0 Clock Overflow Period* (when φ = 20 MHz and φSUB = 32.768 kHz) 0 0 0 0 φ/2 (Initial value) 25.6 µs 1 φ/64 819.2 µs 0 φ/128 1.6 ms 1 φ/512 6.6 ms 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 0 φ/32768 419.4 ms 1 φ/131072 1.68 s 0 φSUB/2 15.6 ms 1 φSUB/4 31.3 ms 0 φSUB/8 62.
PAGE 436
Section 14 Watchdog Timer (WDT) Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to 1 by an external reset, and when the RST/NMI bit is 1, is cleared to 0 by an internal reset due to watchdog timer overflow. Bit 3 XRST Description 0 Reset is generated by watchdog timer overflow 1 Reset is generated by external reset input 14.2.
PAGE 437
Section 14 Watchdog Timer (WDT) 14.3 Operation 14.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, an internal reset or NMI interrupt request is generated.
PAGE 438
Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 H'00 written to TCNT OVF = 1* WT/IT = 1 H'00 written TME = 1 to TCNT Internal reset signal 518 system clock periods Legend: WT/IT: Timer mode select bit TME: Timer enable bit OVF: Overflow flag Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0. Figure 14.3 Operation in Watchdog Timer Mode 14.3.
PAGE 439
Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 14.4 Operation in Interval Timer Mode 14.3.3 Timing of Setting of Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 14.5.
PAGE 440
Section 14 Watchdog Timer (WDT) 14.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request. 14.5 Usage Notes 14.5.
PAGE 441
Section 14 Watchdog Timer (WDT) 14.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 14.5.
PAGE 442
Section 14 Watchdog Timer (WDT) 14.5.5 OVF Flag Clear Condition To clear OVF flag in WOVI handling routine, read TCSR when OVF=1, then write with 0 to OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR read is occurred, OVF=1 is read but OVF can not be cleared by writing with 0 to OVF. In this case, reading TCSR when OVF=1 two times meet the requirements of OVF clear condition. Please read TCSR when OVF=1 two times before writing with 0 to OVF.
PAGE 443
Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) 15.1 Overview The H8S/2138 Group and H8S/2134 Group are equipped with a 3-channel serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
PAGE 444
Section 15 Serial Communication Interface (SCI, IrDA)  One serial data transfer format Data length: 8 bits  Receive error detection: Overrun errors detected • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • LSB-first or MSB-first transfer can be selecte
PAGE 445
Section 15 Serial Communication Interface (SCI, IrDA) 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI.
PAGE 446
Section 15 Serial Communication Interface (SCI, IrDA) 15.1.3 Pin Configuration Table 15.1 shows the serial pins used by the SCI. Table 15.1 SCI Pins Channel Pin Name Symbol* I/O Function 0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output 1 2 Note: 15.1.
PAGE 447
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 448
Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Register Descriptions 15.2.1 Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU.
PAGE 449
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.3 Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
PAGE 450
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.5 Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times.
PAGE 451
Section 15 Serial Communication Interface (SCI, IrDA) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting.
PAGE 452
Section 15 Serial Communication Interface (SCI, IrDA) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description 0 1 stop bit* 2 2 stop bits* 1 1 (Initial value) Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2.
PAGE 453
Section 15 Serial Communication Interface (SCI, IrDA) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.8, Bit Rate Register.
PAGE 454
Section 15 Serial Communication Interface (SCI, IrDA) Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1.
PAGE 455
Section 15 Serial Communication Interface (SCI, IrDA) Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE Description 0 1 Reception disabled* 2 Reception enabled* 1 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode.
PAGE 456
Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 TEIE Description 0 Transmit-end interrupt (TEI) request disabled* Transmit-end interrupt (TEI) request enabled* 1 Note: (Initial value) TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
PAGE 457
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.7 Serial Status Register (SSR) Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times.
PAGE 458
Section 15 Serial Communication Interface (SCI, IrDA) Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
PAGE 459
Section 15 Serial Communication Interface (SCI, IrDA) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER Description 0 [Clearing condition] 1 (Initial value)* When 0 is written in FER after reading FER = 1 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, 2 and the stop bit is 0 * Notes: 1.
PAGE 460
Section 15 Serial Communication Interface (SCI, IrDA) Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified.
PAGE 461
Section 15 Serial Communication Interface (SCI, IrDA) Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted 15.2.
PAGE 462
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) φ = 2 MHz φ = 2.097152 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 150 1 103 0.16 1 300 0 207 0.16 600 0 103 1200 0 2400 4800 φ = 2.4576 MHz N Error (%) –0.04 1 174 108 0.21 1 0 217 0.21 0.16 0 108 0.21 51 0.16 0 54 0 25 0.16 0 0 12 0.
PAGE 463
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) φ = 6 MHz Bit Rate (bits/s) n N Error (%) 110 2 106 150 2 300 φ = 6.144 MHz φ = 7.3728 MHz φ = 8 MHz N Error (%) n N Error (%) –0.44 2 108 0.08 2 130 77 0.16 2 79 0.00 2 1 155 0.16 1 159 0.00 1 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.
PAGE 464
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) φ = 14 MHz φ = 14.7456 MHz Bit Rate (bits/s) n N Error (%) 110 2 248 150 2 300 φ = 16 MHz φ = 17.2032 MHz N Error (%) n N Error (%) n N Error (%) –0.17 3 64 0.70 3 70 0.03 3 75 0.48 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.
PAGE 465
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode) Operating Frequency φ (MHz) φ = 2 MHz Bit Rate φ = 4 MHz (bits/s) n N n N 110 3 70 — — 250 2 124 2 500 1 249 2 1k 1 124 2.
PAGE 466
Section 15 Serial Communication Interface (SCI, IrDA) The BRR setting is found from the following equations. Asynchronous mode: N= φ 64 × 22n–1 ×B × 106 – 1 Synchronous mode: N= Where B: N: φ: n: φ × 106 – 1 8 × 22n–1 × B Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.
PAGE 467
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.
PAGE 468
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.
PAGE 469
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 15.2.
PAGE 470
Section 15 Serial Communication Interface (SCI, IrDA) Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR.
PAGE 471
Section 15 Serial Communication Interface (SCI, IrDA) MSTPCRL Bit 7—Module Stop (MSTP7): Specifies the SCI0 module stop mode. MSTPCRL Bit 7 MSTP7 Description 0 SCI0 module stop mode is cleared 1 SCI0 module stop mode is set (Initial value) MSTPCRL Bit 6—Module Stop (MSTP6): Specifies the SCI1 module stop mode. MSTPCRL Bit 6 MSTP6 Description 0 SCI1 module stop mode is cleared 1 SCI1 module stop mode is set (Initial value) MSTPCRL Bit 5—Module Stop (MSTP5): Specifies the SCI2 module stop mode.
PAGE 472
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.11 Keyboard Comparator Control Register (KBCOMP) 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KBCOMP is an 8-bit readable/writable register that selects the functions of SCI2 and the A/D converter. KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
PAGE 473
Section 15 Serial Communication Interface (SCI, IrDA) 15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 15.8.
PAGE 474
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 475
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
PAGE 476
Section 15 Serial Communication Interface (SCI, IrDA) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR. Table 15.
PAGE 477
Section 15 Serial Communication Interface (SCI, IrDA) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
PAGE 478
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0.
PAGE 479
Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] Initialization Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 480
Section 15 Serial Communication Interface (SCI, IrDA) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
PAGE 481
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.
PAGE 482
Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
PAGE 483
Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.7 Sample Serial Reception Data Flowchart (cont) Rev. 4.
PAGE 484
Section 15 Serial Communication Interface (SCI, IrDA) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in RSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a.
PAGE 485
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 486
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
PAGE 487
Section 15 Serial Communication Interface (SCI, IrDA) Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: receiving station specification (MPB = 0) Data transmission cycle: data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.
PAGE 488
Section 15 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, one frame of 1s is output and transmission is enabled.
PAGE 489
Section 15 Serial Communication Interface (SCI, IrDA) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
PAGE 490
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.11 shows an example of SCI operation for transmission using a multiprocessor format.
PAGE 491
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start reception Read MPIE bit in SCR Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
PAGE 492
Section 15 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev. 4.
PAGE 493
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.13 shows an example of SCI operation for multiprocessor format reception.
PAGE 494
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock.
PAGE 495
Section 15 Serial Communication Interface (SCI, IrDA) Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
PAGE 496
Section 15 Serial Communication Interface (SCI, IrDA) [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Start initialization Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used.
PAGE 497
Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Transmission (Synchronous Mode): Figure 15.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
PAGE 498
Section 15 Serial Communication Interface (SCI, IrDA) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
PAGE 499
Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.17 Example of SCI Operation in Transmission Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial reception.
PAGE 500
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error handling (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
PAGE 501
Section 15 Serial Communication Interface (SCI, IrDA) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
PAGE 502
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 503
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.5 IrDA Operation Figure 15.21 shows a block diagram of the IrDA function. When the IrDA function is enabled with bit IrE in KBCOMP, the SCI channel 2 TxD2 and RxD2 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins).
PAGE 504
Section 15 Serial Communication Interface (SCI, IrDA) The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set as the minimum high-level pulse width at 1.41 µs or above. When the serial data is 1, no pulse is output.
PAGE 505
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.12 Bit IrCKS2 to IrCKS0 Settings Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.26 1.63 2 010 010 010 010 010 — 2.097152 010 010 010 010 010 — 2.4576 010 010 010 010 010 — 3 011 011 011 011 011 — 3.6864 011 011 011 011 011 011 4.
PAGE 506
Section 15 Serial Communication Interface (SCI, IrDA) 15.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR.
PAGE 507
Section 15 Serial Communication Interface (SCI, IrDA) TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance, and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be accepted in this case. 15.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR.
PAGE 508
Section 15 Serial Communication Interface (SCI, IrDA) Break Detection and Processing: When a framing error (FER) is detected, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
PAGE 509
Section 15 Serial Communication Interface (SCI, IrDA) 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by equation (1) below. M = 0.5 – Where M: N: D: L: F: 1 D – 0.5 (1 + F) × 100% – (L – 0.5)F – 2N N ..........
PAGE 510
Section 15 Serial Communication Interface (SCI, IrDA) Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24) • When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receivedata-full interrupt (RXI).
PAGE 511
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 2 A two-channel I C bus interface is available as an option in the H8S/2138 Group. The I C bus interface is not available for the H8S/2134 Group. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432137SW 2. The product number is identical for F-ZTAT versions.
PAGE 512
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Wait function in slave mode (I C bus format) 2 A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible.
PAGE 513
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Formatless dedicated clock (channel 0 only) φ PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX Interrupt generator Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SA
PAGE 514
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Vcc VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in H8S/2138 Group chip SCL out SCL out SDA in SDA in SDA out SDA out SCL SDA SDA in SCL SDA SCL out SCL in (Slave 1) (Slave 2) 2 Figure 16.2 I C Bus Interface Connections (Example: H8S/2138 Group Chip as Master) 16.1.3 Input/Output Pins 2 Table 16.1 summarizes the input/output pins used by the I C bus interface. 2 Table 16.
PAGE 515
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.1.4 Register Configuration 2 Table 16.2 summarizes the registers of the I C bus interface. Table 16.
PAGE 516
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.2 Register Descriptions 16.2.
PAGE 517
2 Section 16 I C Bus Interface [H8S/2138 Group Option] ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
PAGE 518
2 Section 16 I C Bus Interface [H8S/2138 Group Option] TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started (Initial value) [Clearing conditions] • When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) • When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected • When a stop condition is detected with the I C bus format selected • In receive mode (TRS
PAGE 519
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.2.2 Slave Address Register (SAR) Bit 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format.
PAGE 520
2 Section 16 I C Bus Interface [H8S/2138 Group Option] DDCSWR Bit 6 SAR Bit 0 SARX Bit 0 SW FS FSX Operating Mode 0 0 0 I C bus format 2 • 1 I C bus format • SAR slave address recognized • SARX slave address ignored 0 I C bus format • SAR slave address ignored • SARX slave address recognized Synchronous serial format • 16.2.
PAGE 521
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to 2 SVAX0, differing from the addresses of other slave devices connected to the I C bus. Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format.
PAGE 522
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 7 MLS Description 0 MSB-first 1 LSB-first (Initial value) Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data 2 and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
PAGE 523
2 Section 16 I C Bus Interface [H8S/2138 Group Option] STCR Bit 5 or 6 Bit 5 Bit 4 Bit 3 Transfer Rate IICX CKS2 CKS1 CKS0 Clock 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: * φ= 5 MHz φ= 8 MHz φ= 10 MHz φ= 16 MHz φ= 20 MHz 0 φ/28 179 kHz 286 kHz 357 kHz 571 kHz* 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 714 kHz* 500 kHz* 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz* 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 φ/80 62.
PAGE 524
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 2 Bit 1 Bit 0 BC2 BC1 BC0 Synchronous Serial Format I C Bus Format 0 0 0 8 9 1 1 2 0 2 3 1 3 4 0 4 5 1 5 6 0 6 7 1 7 8 1 1 0 1 Bits/Frame 2 (Initial value) 2 16.2.5 I C Bus Control Register (ICCR) Bit 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/(W)* W Note: * Only 0 can be written, to clear the flag.
PAGE 525
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 7 ICE Description 0 I C bus interface module disabled, with SCL and SDA signal pins set to port function (Initial value) 2 2 Internal state initialization of I C bus interface module SAR and SARX can be accessed 2 1 I C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed 2 2 Bit 6—I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C bus
PAGE 526
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 5 Bit 4 MST TRS Operating Mode 0 0 Slave receive mode 1 Slave transmit mode 0 Master receive mode 1 Master transmit mode 1 (Initial value) Bit 5 MST Description 0 Slave mode (Initial value) [Clearing conditions] 1. When 0 is written by software 2 2. When bus arbitration is lost after transmission is started in I C bus format master mode 1 Master mode [Setting conditions] 1.
PAGE 527
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the 2 acknowledge bit returned from the receiving device when using the I C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0.
PAGE 528
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0.
PAGE 529
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 1 IRIC Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) 1 Interrupt requested [Setting conditions] • I2C bus format master mode 1.
PAGE 530
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
PAGE 531
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored.
PAGE 532
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been 2 detected during frame transfer in I C bus format slave mode. Bit 7 ESTP Description 0 No error stop condition (Initial value) [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2.
PAGE 533
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Bit 5—I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag 2 (IRTR): Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time.
PAGE 534
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 4 AASX Description 0 Second slave address not recognized (Initial value) [Clearing conditions] 1. When 0 is written in AASX after reading AASX = 1 2. When a start condition is detected 3. In master mode 1 Second slave address recognized [Setting condition] When the second slave address is detected in slave receive mode while FSX = 0 Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode.
PAGE 535
2 Section 16 I C Bus Interface [H8S/2138 Group Option] AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 2 AAS Description 0 Slave address or general call address not recognized (Initial value) [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AAS after reading AAS = 1 3.
PAGE 536
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read.
PAGE 537
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Bits 6 and 5—I C Transfer Select 1 and 0 (IICX1, IICX0): These bits, together with bits CKS2 to CKS0 in ICMR of IIC1, select the transfer rate in master mode. For details, see section 16.2.4, 2 I C Bus Mode Register (ICMR). 2 2 Bit 4—I C Master Enable (IICE): Controls CPU access to the I C bus interface data and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
PAGE 538
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 7—DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC 2 channel 0 from formatless mode to the I C bus format.
PAGE 539
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the CPU when automatic format switching is executed for IIC channel 0.
PAGE 540
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.2.
PAGE 541
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3 Operation 16.3.1 I C Bus Data Format 2 2 2 The I C bus interface has serial and I C bus formats. 2 The I C bus formats are addressing formats with an acknowledge bit. These are shown in (a) and (b) in figure 16.3. The first frame following a start condition always consists of 8 bits. IIC channel 0 only is capable of formatless operation, as shown in figure 16.4. The serial format is a non-addressing format with no acknowledge bit.
PAGE 542
2 Section 16 I C Bus Interface [H8S/2138 Group Option] IIC0 only, FS = 0 or FSX = 0 DATA A 8 1 DATA n A A/A 1 1 1 transfer bit count (n = 1 to 8) m transfer frame count (m ≥ 1) Note: This mode applies to the DDC (Display Data Channel) which is a PC monitoring system standard. Figure 16.4 Formatless FS = 1 and FSX = 1 S DATA DATA P 1 8 n 1 1 m transfer bit count (n = 1 to 8) transfer frame count (m ≥ 1) 2 Figure 16.
PAGE 543
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Table 16.4 I C Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address, by which the master device selects a slave device R/W Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 A Acknowledge.
PAGE 544
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no interrupt is inserted. If a period of time that is equal to transfer one byte has elapsed by the time the IRlC flag is cleared, the end of transfer cannot be identified. The master device sequentially sends the transmit clock and the data written to ICDR with the timing shown in figure 16.7. The selected slave device (i.e.
PAGE 545
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Start condition generation SCL (master output) 1 SDA (master output) bit 7 2 bit 6 3 bit 5 4 bit 4 5 bit 3 6 bit 2 bit 1 8 1 9 2 bit 7 bit 0 R/W Slave address SDA (slave output) 7 [7] bit 6 Data 1 A [5] IRIC IRTR ICDR address + R/W Note: Data write timing in ICDR ICDR Writing prohibited Data 1 ICDR Writing enable User processing [4] Write BBSY = 1 and SCP = 0 (start condition issuance) [6] ICDR write [6] IRIC clear [9] I
PAGE 546
2 Section 16 I C Bus Interface [H8S/2138 Group Option] [3] The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. If the first frame is the final reception frame, execute the end processing as described in [10]. [4] Clear the IRIC flag to 0 to release from the wait state.
PAGE 547
2 Section 16 I C Bus Interface [H8S/2138 Group Option] then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be generated.) [14] Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and generates the stop condition.
PAGE 548
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode.
PAGE 549
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Start condition generation SCL (master output) 1 2 3 Bit 7 Bit 6 Bit 5 4 5 6 Bit 4 Bit 3 Bit 2 7 8 9 1 2 SCL (slave output) SDA (master output) Slave address SDA (slave output) Bit 1 Bit 0 R/W Bit 7 Bit 6 Data 1 [4] A RDRF IRIC Interrupt request generation ICDRS Address + R/W ICDRR User processing Address + R/W [5] ICDR read [5] IRIC clear Figure 16.
PAGE 550
2 Section 16 I C Bus Interface [H8S/2138 Group Option] SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 3 4 5 6 7 8 9 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCL (slave output) SDA (master output) Data 1 SDA (slave output) Bit 7 Bit 6 [4] Data 2 A [4] A RDRF IRIC ICDRS Data 1 ICDRR Data 1 User processing Interrupt request generation Interrupt request generation [5] ICDR read Data 2 Data 2 [5] IRIC clear Figure 16.
PAGE 551
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode.
PAGE 552
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Slave receive mode SCL (master output) 8 Slave transmit mode 9 1 2 3 4 5 6 7 8 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 SCL (slave output) SDA (slave output) SDA (master output) R/W Bit 7 Data 1 [2] Bit 6 Data 2 A TDRE Interrupt request generation IRIC [3] Interrupt request generation Interrupt request generation Data 1 ICDRT ICDRS Data 2 Data 2 Data 1 User processing [3] IRIC [3] ICDR write clea
PAGE 553
2 Section 16 I C Bus Interface [H8S/2138 Group Option] (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA 8 A 1 IRIC Clear IRIC User processing Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA
PAGE 554
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3.7 2 Automatic Switching from Formatless Mode to I C Bus Format Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating 2 mode. Switching from formatless mode to the I C bus format (slave mode) is performed automatically when a falling edge is detected on the SCL pin.
PAGE 555
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3.8 Operation Using the DTC 2 The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.5 shows some examples of processing using the DTC.
PAGE 556
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
PAGE 557
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Start [1] Initialize Initialize [2] Test the status of the SCL and SDA lines. Read BBSY in ICCR No BBSY = 0? Yes [3] Select master transmit mode. Set MST = 1 and TRS = 1 in ICCR [4] Start condition issuance Write BBSY = 1 and SCP = 0 in ICCR [5] Wait for a start condition generation Read IRIC in ICCR No IRIC = 1? Yes [6] Set transmit data for the first byte (slave address + R/W).
PAGE 558
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Master receive mode Set TRS = 0 in ICCR [1] Select receive mode Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. Read ICDR Clear IRIC in ICCR [3] Wait for 1 byte to be received. (8th clock falling edge) Read IRIC in ICCR No IRIC=1? Yes Last receive ? Yes No No Clear IRIC in ICCR [4] Clear IRIC to trigger the 9th clock.
PAGE 559
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR [2] No IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). Clear IRIC in ICCR [3] Start receiving.
PAGE 560
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR [1] [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Clear IRIC in ICCR [3] Test for end of transfer. [4] Select slave receive mode. Read IRIC in ICCR No [2] [5] Dummy read (to release the SCL line).
PAGE 561
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 16.3.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR register or clearing ICE bit. For details of CLR3 to CLR0 bits setting, see section 16.2.8, DDC Switch Register (DDCSWR).
PAGE 562
2 Section 16 I C Bus Interface [H8S/2138 Group Option] The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1.
PAGE 563
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Table 16.6 I C Bus Timing (SCL and SDA Output) Item Symbol Output Timing Unit Notes SCL output cycle time tSCLO 28tcyc to 256tcyc ns SCL output high pulse width tSCLHO 0.5tSCLO ns Figure 25.26 (reference) SCL output low pulse width tSCLLO 0.5tSCLO ns SDA output bus free time tBUFO 0.5tSCLO – 1tcyc ns Start condition output hold time tSTAHO 0.
PAGE 564
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Table 16.7 Permissible SCL Rise Time (tSr) Values Time Indication 2 IICX tcyc Indication 0 7.5tcyc 1 17.5tcyc I C Bus Specification φ = (Max.
PAGE 565
2 Section 16 I C Bus Interface [H8S/2138 Group Option] 2 Table 16.8 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] 2 Item tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tcyc Indication φ= 8 MHz φ= φ= φ= 10 MHz 16 MHz 20 MHz –1000 4000 4000 4000 4000 4000 4000 High-speed –300 mode 600 950 950 950 950 950 Standard mode –250 4700 4750 4750 4750 4750 4750 High-speed –250 mode 1300 1 1 1 1 1 1000* 1000* 1000* 1000* 1000* 0.
PAGE 566
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Time Indication (at Maximum Transfer Rate) [ns] 2 Item tcyc Indication tSDAHO 3tcyc I C Bus SpecifitSr/tSf Influence cation φ = (Max.) (Min.) 5 MHz φ= 8 MHz φ= φ= φ= 10 MHz 16 MHz 20 MHz 0 0 600 375 300 188 150 High-speed 0 mode 0 600 375 300 188 150 Standard mode 2 Notes: 1. Does not meet the I C bus interface specification.
PAGE 567
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register).
PAGE 568
2 Section 16 I C Bus Interface [H8S/2138 Group Option] [1] Wait for end of 1-byte transfer IRIC=1 ? No [1] [2] Determine wheter SCL is low Yes Clear IRIC in ICSR Start condition issuance? [3] Issue restart condition instruction for transmission No Other processing [4] Determine whether start condition is generated or not Yes Read SCL pin SCL=Low ? [2] [5] Set transmit data (slave address + R/W) No Note: Program so that processing instruction from [3] to [5] is Yes executed continuously.
PAGE 569
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Note on I C Bus Interface Stop Condition Instruction Issuance 2 If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large, or if there is a slave devices of the type that drives SCL low to effect a wait, after rising of the 9th SCL clock, issue the stop condition after reading SCL and determining it to be low, as shown below.
PAGE 570
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Notes on WAIT Function  Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall.
PAGE 571
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Notes on ICDR Reads and ICCR Access in Slave Transmit Mode 2 In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 16.22.
PAGE 572
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.23) 2 in the slave mode of the I C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. However, at other times (indicated as (b) in figure 16.
PAGE 573
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Notes on Arbitration Lost in Master Mode 2 The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address.
PAGE 574
2 Section 16 I C Bus Interface [H8S/2138 Group Option] (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. • Notes on Interrupt Occurrence after ACKB Reception  Conditions to cause this failure The IRIC flag is set to 1 when both of the following conditions are satisfied.
PAGE 575
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Master transmit mode or slave transmit mode Stop condition Slave reception mode Start condition (2) Address that does not match is received. SDA N SCL 8 Address 1 9 2 3 4 5 6 7 8 A Data 9 1 2 ACKB bit IRIC flag Stop condition detection (1) Acknowledge bit is received and the ACKB bit is set to 1. Countermeasure: Clear the ACKE bit to 0 to clear the ACKB bit. (3) Unnecessary interrupt occurs (received address is invalid).
PAGE 576
2 Section 16 I C Bus Interface [H8S/2138 Group Option] • Notes on TRS Bit Setting and ICDR Register Access Conditions to cause this failure Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are satisfied.  Master mode Figure 16.26 shows the notes on ICDR reading (TRS = 1) in master mode. (1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full). (2) Reads ICDR register after switching to transmit mode (TRS = 1).
PAGE 577
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Along with ICDRS: ICDRR transfer Stop condition SDA Cancel condition of SCL = Low fixation is set. Start condition Address A SCL 8 1 9 2 3 4 5 6 7 8 A Data 9 1 2 3 (3) TRS = 0 TRS bit (2) RDRF = 0 RDRF bit ICDRS data full (1) ICDRS data full TRS = 0 setting ICDR read Detection of 9th clock rise (TRS = 1) Figure 16.
PAGE 578
2 Section 16 I C Bus Interface [H8S/2138 Group Option] Rev. 4.
PAGE 579
Section 17 Host Interface [H8S/2138 Group] Section 17 Host Interface [H8S/2138 Group] Provided in the H8S/2138 Group; not provided in the H8S/2134 Group. 17.1 Overview The H8S/2138 Group has an on-chip host interface (HIF) that enables connection to an ISA bus, widely used as the internal bus in personal computers. The host interface provides a dual-channel parallel interface between the on-chip CPU and a host processor. The host interface is available only when the HI12E bit is set to 1 in SYSCR2.
PAGE 580
Section 17 Host Interface [H8S/2138 Group] 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the host interface.
PAGE 581
Section 17 Host Interface [H8S/2138 Group] 17.1.3 Input and Output Pins Table 17.1 lists the input and output pins of the host interface module. Table 17.
PAGE 582
Section 17 Host Interface [H8S/2138 Group] 17.1.4 Register Configuration Table 17.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1, ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR. Table 17.
PAGE 583
Section 17 Host Interface [H8S/2138 Group] 17.2 Register Descriptions 17.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W SYSCR is an 8-bit readable/writable register which controls H8S/2138 Group chip operations. Of the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be accessed when the HIE bit is set to 1.
PAGE 584
Section 17 Host Interface [H8S/2138 Group] 17.2.2 System Control Register 2 (SYSCR2) Bit 7 6 5 4 3 2 1 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface functions are enabled or disabled by the HI12E bit in SYSCR2. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
PAGE 585
Section 17 Host Interface [H8S/2138 Group] Bit 0 HI12E Description 0 Host interface functions are disabled 1 Host interface functions are enabled 17.2.
PAGE 586
Section 17 Host Interface [H8S/2138 Group] Bit 0—Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using firmware to manipulate the P81 output. Bit 0 FGA20E Description 0 Fast A20 gate function is disabled 1 Fast A20 gate function is enabled 17.2.
PAGE 587
Section 17 Host Interface [H8S/2138 Group] 17.2.6 Status Register 1 (STR1) Bit Initial value 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R/(W)* Host Read/Write R R R R R R R R Note: * Only 0 can be written, to clear the flag. STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors.
PAGE 588
Section 17 Host Interface [H8S/2138 Group] Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0 when the host processor reads ODR1. Bit 0 OBF Description 0 [Clearing condition] When the host processor reads ODR1 or the slave writes 0 in the OBF bit (Initial value) 1 [Setting condition] When the slave processor writes to ODR1 Table 17.3 shows the conditions for setting and clearing the STR1 flags. Table 17.
PAGE 589
Section 17 Host Interface [H8S/2138 Group] 17.2.8 Output Data Register 2 (ODR2) Bit Initial value 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 — — — — — — — — Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write R R R R R R R R ODR2 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register to the host processor.
PAGE 590
Section 17 Host Interface [H8S/2138 Group] Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR2. The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals.
PAGE 591
Section 17 Host Interface [H8S/2138 Group] Table 17.
PAGE 592
Section 17 Host Interface [H8S/2138 Group] 17.3 Operation 17.3.1 Host Interface Operation The host interface is activated by setting the HI12E bit (bit 0) to 1 in SYSCR2 in single-chip mode, establishing slave mode. Activation of the host interface (entry to slave mode) appropriates the related I/O lines in port 3 (data), port 8 or 9 (control), and port 4 (host interrupt requests) for interface use. Table 17.5 shows HIF host interface channel selection and pin operation. Table 17.
PAGE 593
Section 17 Host Interface [H8S/2138 Group] Table 17.
PAGE 594
Section 17 Host Interface [H8S/2138 Group] only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the host processor. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 17.7 lists the conditions that set and clear GA20 (P81). Figure 17.2 shows the GA20 output in flowchart form.
PAGE 595
Section 17 Host Interface [H8S/2138 Group] Table 17.
PAGE 596
Section 17 Host Interface [H8S/2138 Group] functions of these pins (input block) are similarly fixed internally. As a result, the host interface I/O pins (HDB7 to HDB0) also go to the high-impedance state. This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the highlevel state, the pins are restored to their normal operation as host interface pins. Table 17.9 shows the scope of HIF pin shutdown in slave mode. Table 17.
PAGE 597
Section 17 Host Interface [H8S/2138 Group] 17.4 Interrupts 17.4.1 IBF1, IBF2 The host interface can issue two interrupt requests to the slave CPU: IBF1 and IBF2. They are input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is enabled when the corresponding enable bit is set. Table 17.10 Input Buffer Full Interrupts Interrupt Description IBF1 Requested when IBFIE1 is set to 1 and IDR1 is full IBF2 Requested when IBFIE2 is set to 1 and IDR2 is full 17.4.
PAGE 598
Section 17 Host Interface [H8S/2138 Group] Slave CPU Master CPU Write to ODR Write 1 to P4DR No HIRQ output high Interrupt initiation HIRQ output low ODR read P4DR = 0? Yes No All bytes transferred? Yes Hardware operations Software operations Figure 17.
PAGE 599
Section 18 D/A Converter Section 18 D/A Converter 18.1 Overview The H8S/2138 Group and H8S/2134 Group have an on-chip D/A converter module with two channels. 18.1.1 Features Features of the D/A converter module are listed below. • Eight-bit resolution • Two-channel output • Maximum conversion time: 10 µs (with 20-pF load capacitance) • Output voltage: 0 V to AVCC • D/A output retention in software standby mode Rev. 4.
PAGE 600
Section 18 D/A Converter 18.1.2 Block Diagram Module data bus Bus interface Figure 18.1 shows a block diagram of the D/A converter. DACR 8-bit D/A DA1 DADR1 DA0 DADR0 AVCC AVSS Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 18.1 Block Diagram of D/A Converter Rev. 4.
PAGE 601
Section 18 D/A Converter 18.1.3 Input and Output Pins Table 18.1 lists the input and output pins used by the D/A converter module. Table 18.1 Input and Output Pins of D/A Converter Module Name Abbreviation I/O Function Analog supply voltage AVCC Input Power supply for analog circuits Analog ground AVSS Input Ground and reference voltage for analog circuits Analog output 0 DA0 Output Analog output channel 0 Analog output 1 DA1 Output Analog output channel 1 18.1.
PAGE 602
Section 18 D/A Converter 18.2 Register Descriptions 18.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin.
PAGE 603
Section 18 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 Analog output DA0 is disabled 1 D/A conversion is enabled on channel 0. Analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1.
PAGE 604
Section 18 D/A Converter 18.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
PAGE 605
Section 18 D/A Converter 18.3 Operation The D/A converter module has two on-chip D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 18.2 shows the timing.
PAGE 606
Section 18 D/A Converter Rev. 4.
PAGE 607
Section 19 A/D Converter Section 19 A/D Converter 19.1 Overview The H8S/2138 Group and H8S/2134 Group incorporate a 10-bit successive-approximations A/D converter that allows up to eight analog input channels to be selected. In addition to the eight analog input channels, up to 8 channels of digital input can be selected for A/D conversion.
PAGE 608
Section 19 A/D Converter 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the A/D converter.
PAGE 609
Section 19 A/D Converter 19.1.3 Pin Configuration Table 19.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 19.
PAGE 610
Section 19 A/D Converter 19.1.4 Register Configuration Table 19.2 summarizes the registers of the A/D converter. Table 19.
PAGE 611
Section 19 A/D Converter 19.2 Register Descriptions 19.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
PAGE 612
Section 19 A/D Converter 19.2.2 A/D Control/Status Register (ADCSR) Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written in bit 7, to clear the flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
PAGE 613
Section 19 A/D Converter Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 A/D conversion stopped 1 Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends (Initial value) Scan mode: A/D conversion is started.
PAGE 614
Section 19 A/D Converter Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channel(s). One analog input channel can be switched to digital input. Only set the input channel while conversion is stopped.
PAGE 615
Section 19 A/D Converter Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped.
PAGE 616
Section 19 A/D Converter Bit 3 Bit 2 Bit 1 Bit 0 KBADE KBCH2 KBCH1 KBCH0 A/D Converter Channel 6 Input A/D Converter Channel 7 Input 0 — — — AN6 AN7 1 0 0 0 CIN0 Undefined 1 CIN1 Undefined 0 CIN2 Undefined 1 CIN3 Undefined 0 CIN4 Undefined 1 CIN5 Undefined 1 1 0 1 19.2.
PAGE 617
Section 19 A/D Converter 19.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP.
PAGE 618
Section 19 A/D Converter 19.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.
PAGE 619
Section 19 A/D Converter Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 19.
PAGE 620
Section 19 A/D Converter 19.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately.
PAGE 621
Section 19 A/D Converter Continuous A/D conversion execution Clear*1 Set*1 ADST Clear*1 ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer ADDRA A/D conversion result 1 ADDRB A/D conversion result 4 A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1.
PAGE 622
Section 19 A/D Converter (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 19.5 A/D Conversion Timing Table 19.
PAGE 623
Section 19 A/D Converter 19.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit is set to 1 by software. Figure 19.6 shows the timing. φ ADTRG Internal trigger signal ADST A/D conversion Figure 19.
PAGE 624
Section 19 A/D Converter 19.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: 1. Analog input voltage range The voltage applied to the ANn analog input pins during A/D conversion should be in the range AVSS ≤ ANn ≤ AVCC (n = 0 to 7). 2. Digital input voltage range The voltage applied to the CINn digital input pins should be in the range AVSS ≤ CINn ≤ AVCC and VSS ≤ CINn ≤ VCC (n = 0 to 7). 3.
PAGE 625
Section 19 A/D Converter (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC 100 Ω Rin*2 AN0 to AN7 *1 0.1 µF AVSS Notes: Figures are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 19.7 Example of Analog Input Protection Circuit Table 19.
PAGE 626
Section 19 A/D Converter A/D Conversion Precision Definitions: H8S/2138 Group and H8S/2134 Group A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 19.10).
PAGE 627
Section 19 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 19.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 19.10 A/D Conversion Precision Definitions (2) Rev. 4.
PAGE 628
Section 19 A/D Converter Permissible Signal Source Impedance: H8S/2138 Group and H8S/2134 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ (Vcc = 4.0 to 5.5 V, when φ ≤ 12 MHz or CKS = 0) or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ (Vcc = 4.0 to 5.
PAGE 629
Section 20 RAM Section 20 RAM 20.1 Overview The H8S/2138, H8S/2134, and H8S/2133 have 4 kbytes of on-chip high-speed static RAM, and the H8S/2137, H8S/2132, and H8S/2130 have 2 kbytes. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 20.1.
PAGE 630
Section 20 RAM 20.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 20.1 shows the register configuration. Table 20.1 Register Configuration Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'09 H'FFC4 Note: 20.2 * Lower 16 bits of the address.
PAGE 631
Section 20 RAM 20.3 Operation 20.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1)) When the RAME bit is set to 1, accesses to H8S/2138, H8S/2134, and H8S/2133 addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2137, H8S/2132, and H8S/2130 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM.
PAGE 632
Section 20 RAM Rev. 4.
PAGE 633
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.1 Overview The H8S/2138 and H8S/2134 have 128 kbytes of on-chip ROM, the H8S/2133 has 96 kbytes, the H8S/2137 and H8S/2132 have 64 kbytes, and the H8S/2130 has 32 kbytes. The ROM is connected to the CPU by a 16-bit data bus.
PAGE 634
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.1.2 Register Configuration The H8S/2138 Group and H8S/2134 Group on-chip ROM is controlled by the operating mode and register MDCR. The register configuration is shown in table 21.1. Table 21.1 ROM Register Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined Depends on the operating mode H'FFC5 Note: * Lower 16 bits of the address. 21.
PAGE 635
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
PAGE 636
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.4 Overview of Flash Memory 21.4.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units).
PAGE 637
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.4.
PAGE 638
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 21.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
PAGE 639
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) On-Board Programming Modes • Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. 2.
PAGE 640
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) • User program mode 1. Initial state (1) The program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2.
PAGE 641
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify Entire memory erase Program/program-verify Note: * To be provided by the user, in accordance with the recommended algorithm.
PAGE 642
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.4.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 21.3. Table 21.
PAGE 643
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.5 Register Descriptions 21.5.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1.
PAGE 644
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.
PAGE 645
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When SWE = 1, and PSU = 1 21.5.
PAGE 646
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Bit 7 FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 21.8.
PAGE 647
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit 7 6 5 4 3 2 1 0 EBR1 — — — — — — EB9/—* EB8/—* Initial value 0 0 0 0 0 0 Read/Write — — — — — — 0 0 1 2 1 2 * * R/W R/W* * Bit 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write 1 R/W* R/W R/W R/W R/W R/W R/W R/W EBR2 2 2 Notes: 1.
PAGE 648
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Table 21.
PAGE 649
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained.
PAGE 650
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
PAGE 651
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate MCU measures low period of H'00 data transmitted by host MCU calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmi
PAGE 652
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 Low period (9 bits) measured (H'00 data) D7 Stop bit High period (1 or more bits) Figure 21.9 RxD1 Input Signal When Using Automatic SCI Bit Rate Adjustment When boot mode is initiated, the H8S/2138 or H8S/2134 Group MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
PAGE 653
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot program, as shown in figure 21.10.
PAGE 654
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board.
PAGE 655
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board supply of programming data, and storing a program/erase control program in part of the program area as necessary.
PAGE 656
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
PAGE 657
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) µs. 21.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
PAGE 658
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Start Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
PAGE 659
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 21.13.
PAGE 660
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Start *1 Set SWE bit in FLMCR1 Wait (x) µs *5 n=1 Set EBR1, EBR2 *3 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *5 Start of erase Set E bit in FLMCR1 Wait (z) ms *5 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *5 Clear ESU bit in FLMCR2 Wait (β) µs *5 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *5 Set block start address to verify address H'FF dummy write to verify address Increment addres
PAGE 661
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
PAGE 662
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Table 21.9 Software Protection Functions Item Description Program Erase SWE bit protection • Yes Yes — Yes Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection 21.8.3 • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2).
PAGE 663
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Figure 21.14 shows the flash memory state transition diagram.
PAGE 664
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.9 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased 1 (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation. There are three reasons for this: 1.
PAGE 665
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.10 Flash Memory Programmer Mode 21.10.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 1281 3 2 3 kbyte* * or 64-kbyte* * on-chip flash memory.
PAGE 666
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.10.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer to match the package concerned. Socket adapters are available for each writer manufacturer supporting Renesas Technology microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory. Figure 21.15 shows the memory map in programmer mode. For pin names in programmer mode, see section 1.3.
PAGE 667
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Table 21.11 Settings for Each Operating Mode in Programmer Mode Pin Names Mode CE OE WE FO7 to FO0 FA17 to FA0 Read L L H Data output Ain* Output disable L H H Hi-Z X Command write 1 Chip disable* L H L Data input Ain* H X X Hi-Z X 2 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2.
PAGE 668
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Table 21.13 AC Characteristics in Memory Read Mode Conditions: VCC = 5.
PAGE 669
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Table 21.14 AC Characteristics When Entering Another Mode from Memory Read Mode Conditions: VCC = 5.
PAGE 670
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Table 21.15 AC Characteristics in Memory Read Mode Conditions: VCC = 5.
PAGE 671
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.10.5 Auto-Program Mode AC Characteristics Table 21.16 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.
PAGE 672
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Address stable FA17 to FA0 tceh CE tas tah tnxtc OE tnxtc twep WE FO7 Data transfer 1 byte to 128 bytes tces twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr tf tds tdh Programming normal end identification signal FO6 Programming wait FO7 to FO0 H'40 Data Data FO5 to FO0 = 0 Figure 21.
PAGE 673
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.10.6 Auto-Erase Mode AC Characteristics Table 21.17 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.
PAGE 674
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Notes on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin).
PAGE 675
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) FA17 to FA0 CE tnxtc tce OE WE tnxtc twep tf tf tr toe tdf tr tds tds FO7 to FO0 tceh tces tceh tces tnxtc twep tdh tdh H'71 H'71 Data Note: FO2 and FO3 are undefined. Figure 21.22 Status Read Mode Timing Waveforms Table 21.
PAGE 676
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.10.8 Status Polling • The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 21.20 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0 to FO5 0 0 0 0 21.10.
PAGE 677
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) 21.10.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1.
PAGE 678
Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT) Do not set or clear the SWE bit during program execution in flash memory: Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing).
PAGE 679
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.1 Overview H8S/2138 F-ZTAT A-mask version and H8S/2134 F-ZTAT A-mask version have 128 kbytes of on-chip flash memory. The flash memory is connected to the bus master by a 16-bit data bus. The bus master accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed.
PAGE 680
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.1.2 Register Configuration This group on-chip ROM is controlled by the operating mode and register MDCR. The register configuration is shown in table 22.1. Table 22.1 ROM Register Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined Depends on the operating mode H'FFC5 Note: * Lower 16 bits of the address. 22.2 Register Descriptions 22.2.
PAGE 681
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
PAGE 682
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.4 Overview of Flash Memory 22.4.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
PAGE 683
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 * * Bus interface/controller Operating mode Mode pins * * Flash memory (128 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Note: * These registers are used only in the flash memory version.
PAGE 684
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 22.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
PAGE 685
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) On-Board Programming Modes • Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. 2.
PAGE 686
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) • User program mode 1. Initial state (1) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2.
PAGE 687
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify Entire memory erase Program/program-verify Note: * To be provided by the user, in accordance with the recommended algorithm.
PAGE 688
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.4.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 22.3. Table 22.
PAGE 689
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.5 Register Descriptions 22.5.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1.
PAGE 690
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.
PAGE 691
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When SWE = 1, and PSU = 1 22.5.
PAGE 692
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Bit 7 FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 22.8.
PAGE 693
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit 7 6 5 4 3 2 1 0 EBR1 — — — — — — EB9 EB8 0 2 —* 0 2 —* 0 2 —* 0 2 —* 0 2 —* 0 2 —* 0 0 1 R/W* R/W* 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write 1 R/W* R/W R/W R/W R/W R/W R/W R/W Initial value Read/Write Bit EBR2 1 Notes: 1.
PAGE 694
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.
PAGE 695
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained.
PAGE 696
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
PAGE 697
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate The chip measures low period of H'00 data transmitted by host The chip calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one
PAGE 698
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop bit High period (1 or more bits) Figure 22.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
PAGE 699
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) area can be used when the programming control program transferred into the RAM enters the execution state. A stack area should be set up as required.
PAGE 700
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased.
PAGE 701
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing an on-board means of supplying programming data, and storing a program/erase control program in part of the program area as necessary.
PAGE 702
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
PAGE 703
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z1), (z2) or (z3) µs. 22.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
PAGE 704
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Write pulse application subroutine Sub-routine write pulse Start of programming Start Enable WDT Set SWE bit in FLMCR1 Set PSU bit in FLMCR2 Wait (x) µs Wait (y) µs Store 128-byte program data in program data area and reprogram data area Set P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs m=0 Wait (α) µs Write 128-byte data in RAM reprogram data *1 area consecutively to flash memory Sub-routine-call Write pulse See
PAGE 705
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 22.13.
PAGE 706
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Start *1 Set SWE bit in FLMCR1 Wait (x) µs *5 n=1 Set EBR1, EBR2 *3 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *5 Start of erase Set E bit in FLMCR1 Wait (z) ms *5 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *5 Clear ESU bit in FLMCR2 Wait (β) µs *5 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *5 Set block start address to verify address H'FF dummy write to verify address Wait (ε) µs *5 Read veri
PAGE 707
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
PAGE 708
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.9 Software Protection Functions Item Description Program Erase SWE bit protection • Yes Yes — Yes Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection 22.8.3 • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2).
PAGE 709
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Figure 22.14 shows the flash memory state transition diagram.
PAGE 710
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.9 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased 1 (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation. There are three reasons for this: 1.
PAGE 711
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.10 Flash Memory Programmer Mode 22.10.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 128kbyte on-chip flash memory*. For precautions concerning the use of programmer mode, see section 22.
PAGE 712
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.10.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer to match the package concerned. Socket adapters are available for each writer manufacturer supporting Renesas Technology microcomputer device types with 128-kbyte on-chip flash memory. Figure 22.15 shows the memory map in programmer mode. For pin names in programmer mode, see section 1.3.
PAGE 713
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.11 Settings for Each Operating Mode in Programmer Mode Pin Names Mode CE OE WE FO7 to FO0 FA17 to FA0 Read L L H Data output Ain* Output disable L H H Hi-Z X Command write 1 Chip disable* L H L Data input Ain* H X X Hi-Z X 2 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode.
PAGE 714
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.13 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
PAGE 715
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.14 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
PAGE 716
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Table 22.15 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
PAGE 717
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.10.5 Auto-Program Mode AC Characteristics Table 22.16 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
PAGE 718
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Address stable FA17 to FA0 tceh CE tas tah tnxtc OE tnxtc twep WE FO7 Data transfer 1 byte to 128 bytes tces twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr tf tds tdh Programming normal end identification signal FO6 Programming wait FO7 to FO0 H'40 Data Data FO5 to FO0 = 0 Figure 22.
PAGE 719
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.10.6 Auto-Erase Mode AC Characteristics Table 22.17 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.
PAGE 720
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) Notes on Use of Auto-Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin).
PAGE 721
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) FA17 to FA0 CE tnxtc tce OE WE tnxtc twep tf tf tr toe tdf tr tds tds FO7 to FO0 tceh tces tceh tces tnxtc twep tdh tdh H'71 H'71 Data Note: FO2 and FO3 are undefined. Figure 22.22 Status Read Mode Timing Waveforms Table 22.
PAGE 722
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.10.8 Status Polling • The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 22.20 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0 to FO5 0 0 0 0 22.10.
PAGE 723
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) 22.10.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1.
PAGE 724
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version) accessed for verify operations (verification during programming/erasing). Do not clear the SWE bit during a program, erase, or verify operation. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled when programming and erasing flash memory to give priority to program/erase operations. Do not perform additional programming.
PAGE 725
Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator 23.1 Overview The H8S/2138 Group and H8S/2134 Group have an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input circuit, and waveform shaping circuit. 23.1.1 Block Diagram Figure 23.
PAGE 726
Section 23 Clock Pulse Generator 23.1.2 Register Configuration The clock pulse generator is controlled by the standby control register (SBYCR) and low-power control register (LPWRCR). Table 23.1 shows the register configuration. Table 23.1 CPG Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'00 H'FF84 Low-power control register LPWRCR R/W H'00 H'FF85 Note: * Lower 16 bits of the address. 23.2 Register Descriptions 23.2.
PAGE 727
Section 23 Clock Pulse Generator Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is φ/2 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 — — 1 1 0 1 23.2.
PAGE 728
Section 23 Clock Pulse Generator 23.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping resistance Rd according to table 23.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 23.
PAGE 729
Section 23 Clock Pulse Generator Table 23.3 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 12 16 20 RS max (Ω) 500 120 80 70 60 50 40 C0 max (pF) 7 7 7 7 7 7 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 23.4.
PAGE 730
Section 23 Clock Pulse Generator 23.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 23.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode.
PAGE 731
Section 23 Clock Pulse Generator Table 23.4 External Clock Input Conditions VCC = 2.7 to 5.5 V VCC = 5.0 V ±10% Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width tEXL 40 — 20 — ns Figure 23.6 External clock input high pulse width tEXH 40 — 20 — ns External clock rise time tEXr — 10 — 5 ns External clock fall time tEXf — 10 — 5 ns Clock low pulse width tCL 0.4 0.6 0.4 0.
PAGE 732
Section 23 Clock Pulse Generator Table 23.5 External Clock Output Settling Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item External clock output settling delay time Note: * Symbol Min Max Unit Notes * 500 — µs Figure 23.7 tDEXT tDEXT includes RES pulse width (tRESW). VCC 2.7V STBY VIH EXTAL φ (internal or external) RES tDEXT* Note: * tDEXT includes RES pulse width (tRESW). Figure 23.7 External Clock Output Settling Delay Timing Rev. 4.
PAGE 733
Section 23 Clock Pulse Generator 23.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 23.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32 clocks. 23.
PAGE 734
Section 23 Clock Pulse Generator tEXCLH tEXCLL VCC × 0.5 EXCL tEXCLr tEXCLf Figure 23.8 Subclock Input Timing When Subclock Is Not Needed: Do not enable subclock input when the subclock is not needed.
PAGE 735
Section 23 Clock Pulse Generator 23.9 Clock Selection Circuit This circuit selects the system clock used in the MCU. The clock signal generated in the EXTAL/XTAL pin oscillator is selected as the system clock when MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. In sub-active mode, sub-sleep mode, and watch mode, the sub-clock signal input from EXCL pin is selected as the system clock.
PAGE 736
Section 23 Clock Pulse Generator Rev. 4.
PAGE 737
Section 24 Power-Down State Section 24 Power-Down State 24.1 Overview In addition to the normal program execution state, the H8S/2138 Group and H8S/2134 Group have a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2138 Group and H8S/2134 Group operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3.
PAGE 738
Section 24 Power-Down State Table 24.
PAGE 739
Section 24 Power-Down State Program-halted state STBY pin = low Reset state STBY pin = high RES pin = low Hardware standby mode RES pin = high Program execution state SSBY = 0, LSON = 0 High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 Clock switching exception handling after oscillation setting time (STS2 to STS0) SLEEP instruction Any interrupt*3 SLEEP instruction External interrupt*4 SSBY = 1 P
PAGE 740
Section 24 Power-Down State Table 24.
PAGE 741
Section 24 Power-Down State 24.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 24.3 summarizes these registers. Table 24.
PAGE 742
Section 24 Power-Down State Bit 7—Software Standby (SSBY): Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc.
PAGE 743
Section 24 Power-Down State Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master in high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0.
PAGE 744
Section 24 Power-Down State Bit 7 DTON Description 0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) 1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or softwar
PAGE 745
Section 24 Power-Down State Bit 5—Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which the subclock (φSUB) input from the EXCL pin is sampled with the clock (φ) generated by the system clock oscillator. When φ = 5 MHz or higher, clear this bit to 0. Bit 5 NESEL Description 0 Sampling at φ divided by 32 1 Sampling at φ divided by 4 (Initial value) Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin.
PAGE 746
Section 24 Power-Down State Bit 4—Prescaler Select (PSS): Selects the WDT1 TCNT input clock. This bit also controls the operation in a power-down mode transition. The operating mode to which a transition is made after execution of a SLEEP instruction is determined in combination with other control bits. For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status Register (TCSR).
PAGE 747
Section 24 Power-Down State MSTRCRH and MSTPCRL Bits 7 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 24.4 for the method of selecting on-chip supporting modules. MSTPCRH, MSTPCRL Bits 7 to 0 MSTP15 to MSTP0 Description 0 Module stop mode is cleared (Initial value of MSTP15, MSTP14) 1 Module stop mode is set (Initial value of MSTP13 to MSTP0) 24.
PAGE 748
Section 24 Power-Down State Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 24.2 Medium-Speed Mode Transition and Clearance Timing 24.4 Sleep Mode 24.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained.
PAGE 749
Section 24 Power-Down State 24.5 Module Stop Mode 24.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 24.4 shows MSTP bits and the corresponding on-chip supporting modules.
PAGE 750
Section 24 Power-Down State Table 24.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register Bit Module MSTPCRH MSTP15 — MSTP14* Data transfer controller (DTC) MSTP13 16-bit free-running timer (FRT) MSTPCRL Note: 24.5.
PAGE 751
Section 24 Power-Down State 24.6 Software Standby Mode 24.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
PAGE 752
Section 24 Power-Down State 24.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time). Table 24.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 24.
PAGE 753
Section 24 Power-Down State Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation settling time tOSC2 NMI exception handling SLEEP instruction Figure 24.3 Software Standby Mode Application Example 24.6.5 Usage Note In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output.
PAGE 754
Section 24 Power-Down State In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while the chip is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
PAGE 755
Section 24 Power-Down State 24.8 Watch Mode 24.8.1 Watch Mode If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU and all on-chip supporting modules except WDT1 stop.
PAGE 756
Section 24 Power-Down State 24.9 Subsleep Mode 24.9.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop.
PAGE 757
Section 24 Power-Down State 24.10 Subactive Mode 24.10.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode directly. When an interrupt is generated in subsleep mode, a transition is made to subactive mode.
PAGE 758
Section 24 Power-Down State 24.11 Direct Transition 24.11.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, mediumspeed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
PAGE 759
Section 25 Electrical Characteristics Section 25 Electrical Characteristics 25.1 Voltage of Power Supply and Operating Range The power supply voltage and operating range (shaded part) for each product are shown in table 25.1. Table 25.1 Power Supply Voltage and Operating Range (1) Product/ Power supply VCC HD64F2134 5.5 V HD64F2132R Product/ Power supply 5-V version HD64F2138 HD64F2138V HD64F2134V Flash Memory HD64F2132RV Programming 4.5 V 4.0 V Select 5.0 V ± 0.
PAGE 760
Section 25 Electrical Characteristics Table 25.1 Power Supply Voltage and Operating Range (2) Product/ Power supply VCC HD64F2134A 5.5 V 3-V version VCC HD64F2138AV Flash HD64F2134AV Memory Programming 4.5 V 4.0 V Select 3.3 V ± 0.3 V for programing condition in PROM programmer 2 MHz VCC1 pin Product/ Power supply 5-V version HD64F2138A (F-ZTAT A-Mask Products) 5.5 V Select 3.3 V ± 0.3 V for programing condition in PROM programmer 3.6 V Flash Memory Programming 3.0 V 2.
PAGE 761
Section 25 Electrical Characteristics Table 25.1 Power Supply Voltage and Operating Range (4) Product/ Power supply 5-V version (Mask-ROM Products) 4-V version HD6432132 VCC VCC HD6432130 5.5 V 5.5 V 3-V version VCC 5.5 V 4.5 V 4.0 V 2.7 V 2 MHz 20 MHz fop VCC1 pin 2 MHz 16 MHz fop 2 MHz 10 MHz fop VCC = 5.0 V ±10% VCC = 4.0 V to 5.5 V VCC = 2.7 V to 5.5 V AVCC = 5.0 V ±10% AVCC = 4.0 V to 5.5 V AVCC = 2.7 V to 5.5 V VCC2 pin AVCC pin Rev. 4.
PAGE 762
Section 25 Electrical Characteristics 25.2 Electrical Characteristics of H8S/2138 F-ZTAT 25.2.1 Absolute Maximum Ratings Table 25.2 lists the absolute maximum ratings. Table 25.2 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +7.0 V Input voltage (except ports 6 and 7) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.3 V Input voltage (CIN input selected for port 6) Vin Lower voltage of –0.3 to VCC +0.
PAGE 763
Section 25 Electrical Characteristics 25.2.2 DC Characteristics Table 25.3 lists the DC characteristics. Table 25.4 lists the permissible output currents. Table 25.3 DC Characteristics (1) 1 1 9 Conditions: VCC = 5.0 V ±10%, AVCC* = 5.
PAGE 764
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Output high All output pins voltage (except P97, and 4 5 P52* )* 4 P97, P52* VOH VCC –0.5 — — V IOH = –200 µA 3.5 — — V IOH = –1 mA 2.5 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA — — 1.0 V IOL = 10 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.
PAGE 765
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions 1 Analog power supply voltage* AVCC 4.5 — 5.5 V Operating Idle/not used RAM standby voltage VRAM 2.0 — 5.5 V 2.0 — — V Notes: 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC by connection to the power supply (VCC), or some other method. 2.
PAGE 766
Section 25 Electrical Characteristics Table 25.3 DC Characteristics (2) 7 1 1 Conditions: VCC = 4.0 V to 5.5 V* , AVCC* = 4.0 V to 5.5 V, VSS = AVSS* = 0 V, Ta = –20 to 7 7 +75°C* (regular specifications), Ta = –40 to +85°C* (wide-range specifications) Item Schmitt trigger input voltage Symbol (1) P67 to P60 2 6 (KWUL = 00)* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 – VT + VT + – VT – VT – VT + VT + – VT – VT Schmitt trigger input voltage (in level 6 switching)* Max Test Unit Conditions 1.
PAGE 767
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Output high All output pins voltage (except P97, and 4 5 P52* )* VOH VCC –0.5 — — V IOH = –200 µA 3.5 — — V IOH = –1 mA, VCC= 4.5 V to 5.5 V 3.0 — — V IOH = –1 mA, VCC < 4.5 V 2.0 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA — — 1.0 V IOL = 10 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.
PAGE 768
Section 25 Electrical Characteristics Item Analog power supply current During A/D, D/A conversion Symbol Min Typ Max Test Unit Conditions AlCC — 3.2 7.0 mA — 0.01 5.0 µA AVCC = 2.0 V to 5.5 V 4.0 — 5.5 V Operating 2.0 — 5.5 V Idle/not used 2.0 — — V Idle 1 Analog power supply voltage* RAM standby voltage AVCC VRAM Notes: 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used.
PAGE 769
Section 25 Electrical Characteristics Table 25.3 DC Characteristics (3) 7 1 1 Conditions: VCC = 3.0 V to 5.5 V* , AVCC* = 3.0 V to 5.5 V, VSS = AVSS* = 0 V, 7 Ta = –20 to +75°C* Item Schmitt trigger input voltage Schmitt trigger input voltage (in level switching) Symbol Min (1) VT P67 to P60 VCC × 0.2 — 2 6 + (KWUL = 00)* * , VT — — 3 IRQ2 to IRQ0* , + – VT – VT VCC × 0.05 — IRQ5 to IRQ3 – P67 to P60 (KWUL = 01) – VT + VT + – VT – VT P67 to P60 (KWUL = 10) – VT + VT — V VCC × 0.
PAGE 770
Section 25 Electrical Characteristics Symbol Min Typ Max Test Unit Conditions VOL — — 0.4 V IOL = 1.6mA — — 1.0 V IOL = 5 mA (VCC < 4.0 V), IOL = 10 mA (4.0 V ≤ VCC ≤ 5.5 V) — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V Item Output low voltage All output pins* Input leakage current RES 5 Ports 1 to 3 Iin Three-state Ports 1 to 6, 8, 9 leakage current (off state) ITSI — — 1.0 µA Vin = 0.
PAGE 771
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions 1 Analog power supply voltage* AVCC — 5.5 V Operating Idle/not used RAM standby voltage VRAM 3.0 2.0 — 5.5 V 2.0 — — V Notes: 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC by connection to the power supply (VCC), or some other method. 2.
PAGE 772
Section 25 Electrical Characteristics Table 25.4 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
PAGE 773
Section 25 Electrical Characteristics H8S/2138 Group or H8S/2134 Group chip 2 kΩ Port Darlington pair Figure 25.1 Darlington Pair Drive Circuit (Example) H8S/2138 Group or H8S/2134 Group chip 600 Ω Ports 1 to 3 LED Figure 25.2 LED Drive Circuit (Example) Rev. 4.
PAGE 774
Section 25 Electrical Characteristics Table 25.5 Bus Drive Characteristics Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol Schmitt trigger input voltage – VT Min Typ Max Unit Test Conditions VCC × 0.3 — — V VCC = 3.0 V to 5.5 V — — VCC × 0.7 VCC = 3.0 V to 5.5 V VT – VT VCC × 0.05 — — VCC = 3.0 V to 5.5 V Input high voltage VIH VCC × 0.7 — VCC +0.5 Input low voltage VIL –0.5 — VCC × 0.
PAGE 775
Section 25 Electrical Characteristics (1) Clock Timing Table 25.6 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 25.6 Clock Timing Condition A: VCC = 5.
PAGE 776
Section 25 Electrical Characteristics (2) Control Signal Timing Table 25.7 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 25.7 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.
PAGE 777
Section 25 Electrical Characteristics (3) Bus Timing Table 25.8 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 25.8 Bus Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
PAGE 778
Section 25 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × ns tcyc –60 Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × ns tcyc –50 Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × ns tcyc –60 Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
PAGE 779
Section 25 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 25.9 and 25.10 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 25.9 Timing of On-Chip Supporting Modules (1) Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.
PAGE 780
Section 25 Electrical Characteristics Condition A Condition B 20 MHz Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 25.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 25.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 25.
PAGE 781
Section 25 Electrical Characteristics Table 25.9 Timing of On-Chip Supporting Modules (2) Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 V to 5.
PAGE 782
Section 25 Electrical Characteristics 2 Table 25.10 I C Bus Timing Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min Typ Max Unit SCL clock cycle time tSCL 12 — — tcyc SCL clock high pulse width tSCLH 3 — — tcyc SCL clock low pulse width tSCLL 5 — — tcyc SCL, SDA input rise time tSr — — 7.
PAGE 783
Section 25 Electrical Characteristics 25.2.4 A/D Conversion Characteristics Tables 25.11 and 25.12 list the A/D conversion characteristics. Table 25.11 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 784
Section 25 Electrical Characteristics Table 25.12 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 785
Section 25 Electrical Characteristics 25.2.5 D/A Conversion Characteristics Table 25.13 lists the D/A conversion characteristics. Table 25.13 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 786
Section 25 Electrical Characteristics 25.2.6 Flash Memory Characteristics Table 25.14 shows the flash memory characteristics. Table 25.14 Flash Memory Characteristics (Programming/Erasing Operating Range) Conditions (5-V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications) (3-V version): VCC = 3.0 V to 3.
PAGE 787
Section 25 Electrical Characteristics 3. Block erase time (shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = wait time after P-bit setting (z) × maximum programming count (N)) 5. Number of times when the wait time after P-bit setting (z) = 200 µs. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP (max)). 6.
PAGE 788
Section 25 Electrical Characteristics VCC power supply External capacitor for stabilizing power supply VCL 0.47 µF one or two connected in series VSS Product incorporating internal step-down circuit For products incorporating an internal step-down circuit, do not connect the VCL pin to the VCC power supply. (The VCC1 pin must be connected to the VCC power supply as usual.) The power supply stabilization capacitor must be connected to the VCL pin. Use a monolithic ceramic capacitor of 0.
PAGE 789
Section 25 Electrical Characteristics 25.3 Electrical Characteristics of H8S/2138 F-ZTAT (A-Mask Version), and Mask ROM Versions of H8S/2138 and H8S/2137 25.3.1 Absolute Maximum Ratings Table 25.15 lists the absolute maximum ratings. Table 25.15 Absolute Maximum Ratings Item Symbol Value Unit 1 Power supply voltage* 1 Power supply voltage* (3-V version) 2 Power supply voltage* (VCL pin) VCC –0.3 to +7.0 V VCC –0.3 to +4.3 V VCL –0.3 to +4.3 V Input voltage (except ports 6 and 7) Vin –0.
PAGE 790
Section 25 Electrical Characteristics 25.3.2 DC Characteristics Table 25.16 lists the DC characteristics. Table 25.17 lists the permissible output currents. Table 25.16 DC Characteristics (1) 1 1 Conditions: VCC = 5.0 V ±10%, AVCC* = 5.
PAGE 791
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Output high All output pins voltage (except P97, and 4 5 P52* )* 4 P97, P52* VOH VCC –0.5 — — V IOH = –200 µA 3.5 — — V IOH = –1 mA 2.0 — — V IOH = –200 µA, VCC = 4.5 to 5.5 V — — 0.4 V IOL = 1.6 mA — — 1.0 V IOL = 10 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.
PAGE 792
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions 1 Analog power supply voltage* AVCC 4.5 — 5.5 V Operating 2.0 — 5.5 V Idle/not used RAM standby voltage VRAM 2.0 — — V Notes: 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC by connection to the power supply (VCC), or some other method. 2.
PAGE 793
Section 25 Electrical Characteristics Table 25.16 DC Characteristics (2) 1 1 Conditions: VCC = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.
PAGE 794
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Output high All output pins voltage (except P97, and 4 5 P52* )* VOH VCC –0.5 — — V IOH = –200 µA 3.5 — — V IOH = –1 mA, VCC= 4.5 V to 5.5 V 3.0 — — V IOH = –1 mA, VCC < 4.5 V 1.5 — — V IOH = –200 µA, VCC = 4.0 to 5.5 V VOL — — 0.4 V IOL = 1.6 mA — — 1.0 V IOL = 10 mA Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.
PAGE 795
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Normal operation Current 7 dissipation* Sleep mode 8 Standby mode* ICC — 45 58 mA f = 16 MHz Analog power supply current During A/D, D/A conversion AlCC Idle Analog power supply voltage* RAM standby voltage 1 AVCC VRAM — 30 46 mA f = 16 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 3.2 7.0 mA — 0.01 5.0 µA AVCC = 2.0 V to 5.5 V 4.0 — 5.5 V Operating 2.0 — 5.
PAGE 796
Section 25 Electrical Characteristics Table 25.16 DC Characteristics (3) 7 1 1 Conditions: VCC = 2.7 V to 3.6 V* , AVCC* = 2.7 V to 3.6 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Schmitt trigger input voltage Schmitt trigger input voltage (in level 6 switching)* Symbol (1) P67 to P60 2 6 (KWUL = 00)* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 – VT + VT + – VT – VT – P67 to P60 (KWUL = 01) VT + VT + – VT – VT – P67 to P60 (KWUL = 10) VT + VT Test Unit Conditions VCC × 0.
PAGE 797
Section 25 Electrical Characteristics Symbol Min Typ Max Test Unit Conditions VOL — — V — — 1.0 V IOL = 5 mA Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V Item Output low voltage All output pins* Input leakage current RES 5 Ports 1 to 3 0.4 IOL = 1.6mA Three-state Ports 1 to 6, 8, 9 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.
PAGE 798
Section 25 Electrical Characteristics 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs in H8S/2138. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS in H8S/2138. 5. When ICE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC +0.
PAGE 799
Section 25 Electrical Characteristics Table 25.17 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
PAGE 800
Section 25 Electrical Characteristics Table 25.18 Bus Drive Characteristics Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V version), VSS = 0 V, Ta = –20 to +75°C Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol Schmitt trigger input voltage – VT + VT Min Typ Max Unit VCC × 0.3 — — V — — VCC × 0.7 Test Conditions VT – VT VCC × 0.05 — — Input high voltage VIH VCC × 0.7 — VCC +0.5 Input low voltage VIL –0.5 — VCC × 0.
PAGE 801
Section 25 Electrical Characteristics (1) Clock Timing Table 25.19 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 25.19 Clock Timing Condition A: VCC = 5.
PAGE 802
Section 25 Electrical Characteristics (2) Control Signal Timing Table 25.20 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 25.20 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.
PAGE 803
Section 25 Electrical Characteristics (3) Bus Timing Table 25.21 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 25.21 Bus Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
PAGE 804
Section 25 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × ns tcyc –60 Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × ns tcyc –50 Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × ns tcyc –60 Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
PAGE 805
Section 25 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 25.22 and 25.23 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 25.22 Timing of On-Chip Supporting Modules (1) Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.
PAGE 806
Section 25 Electrical Characteristics Condition A Condition B 20 MHz Min Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 25.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 25.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 25.
PAGE 807
Section 25 Electrical Characteristics Table 25.22 Timing of On-Chip Supporting Modules (2) Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 2.7 V to 3.
PAGE 808
Section 25 Electrical Characteristics 2 Table 25.23 I C Bus Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V version), VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min Typ Max Unit SCL clock cycle time tSCL 12 — — tcyc SCL clock high pulse width tSCLH 3 — — tcyc SCL clock low pulse width tSCLL 5 — — tcyc SCL, SDA input rise time tSr — — 7.
PAGE 809
Section 25 Electrical Characteristics 25.3.4 A/D Conversion Characteristics Tables 25.24 and 25.25 list the A/D conversion characteristics. Table 25.24 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 810
Section 25 Electrical Characteristics Table 25.25 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 811
Section 25 Electrical Characteristics 25.3.5 D/A Conversion Characteristics Table 25.26 lists the D/A conversion characteristics. Table 25.26 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 812
Section 25 Electrical Characteristics 25.3.6 Flash Memory Characteristics Table 25.27 shows the flash memory characteristics. Table 25.27 Flash Memory Characteristics (Programming/Erasing Operating Range) Conditions (5-V version): VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) (3-V version): VCC = 3.0 V to 3.
PAGE 813
Section 25 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4.
PAGE 814
Section 25 Electrical Characteristics 25.3.7 Usage Note (1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc.
PAGE 815
Section 25 Electrical Characteristics 25.4 Electrical Characteristics of H8S/2134 F-ZTAT, H8S/2132 F-ZTAT, and Mask ROM Versions of H8S/2132 and H8S/2130 25.4.1 Absolute Maximum Ratings Table 25.28 lists the absolute maximum ratings. Table 25.28 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +7.0 V Input voltage (except ports 6 and 7) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.
PAGE 816
Section 25 Electrical Characteristics 25.4.2 DC Characteristics Table 25.29 lists the DC characteristics. Table 25.30 lists the permissible output currents. Table 25.29 DC Characteristics (1) 1 1 5 Conditions: VCC = 5.0 V ±10%, AVCC* = 5.
PAGE 817
Section 25 Electrical Characteristics Symbol Min Typ Max Test Unit Conditions ITSI — — 1.0 µA Vin = 0.5 to VCC –0.5 V –IP 50 — 300 µA 60 — 500 µA Vin = 0 V, VCC = 5 V ±10% Cin — — 80 pF — — 50 pF P52, P97, P42, P86 — — 20 pF Input pins except (4) above — — 15 pF 75 100 mA f = 20 MHz 60 85 mA f = 20 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 3.2 7.0 mA — 0.01 5.0 µA AVCC= 2.0 V to 5.5 V 4.5 — 5.5 V Operating 2.0 — 5.
PAGE 818
Section 25 Electrical Characteristics Table 25.29 DC Characteristics (2) 5 1 1 Conditions: VCC = 4.0 V to 5.5 V* , AVCC* = 4.0 V to 5.5 V, VSS = AVSS* = 0 V, Ta = –20 to 5 5 +75°C* (regular specifications), Ta = –40 to +85°C* (wide-range specifications) Min Typ Max Test Unit Conditions 1.0 — — V — — VCC × 0.7 V 0.4 — — V 0.8 — — V — — VCC × 0.7 V VT – VT 0.3 — — V VIH VCC –0.7 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Port 7 2.0 — AVCC +0.
PAGE 819
Section 25 Electrical Characteristics Symbol Min Typ Max Test Unit Conditions Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V Item Input leakage current RES Vin = 0.5 to VCC –0.5 V Three-state Ports 1 to 6, 8, 9 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.5 V Input pull-up MOS current –IP 50 — 300 µA Port 6 60 — 500 µA Vin = 0 V, VCC = 4.5 V to 5.
PAGE 820
Section 25 Electrical Characteristics 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 5. Ranges of VCC = 4.5 to 5.
PAGE 821
Section 25 Electrical Characteristics Table 25.29 DC Characteristics (3) 1 Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC* = 2.7 V to 5.5 V, 1 VSS = AVSS* = 0 V, Ta = –20 to +75°C 5 1 (Flash memory version): VCC = 3.0 V to 5.5 V* , AVCC* = 3.0 V to 5.5 V, 1 5 VSS = AVSS* = 0 V, Ta = –20 to +75°C* Item Schmitt trigger input voltage Input high voltage Input low voltage Symbol 2 4 P67 to P60* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 (1) – VT + VT Min Typ Max Test Unit Conditions VCC × 0.
PAGE 822
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Three-state Ports 1 to 6, 8, 9 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.5 V Input pull-up MOS current –IP 10 — 150 µA 30 — 250 µA Vin = 0 V, 5 VCC = 2.7 V* to 3.
PAGE 823
Section 25 Electrical Characteristics 4. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 5. For flash memory program/erase operations, the applicable ranges are VCC = 3.0 V to 3.6 V, Ta = 0 to +75°C. For the F-ZTAT versions, the test condition is VCC = 3.0 V or higher. 6.
PAGE 824
Section 25 Electrical Characteristics Table 25.30 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
PAGE 825
Section 25 Electrical Characteristics (1) Clock Timing Table 25.31 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 25.31 Clock Timing Condition A: VCC = 5.
PAGE 826
Section 25 Electrical Characteristics (2) Control Signal Timing Table 25.32 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 25.32 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.
PAGE 827
Section 25 Electrical Characteristics (3) Bus Timing Table 25.33 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 25.33 Bus Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
PAGE 828
Section 25 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × ns tcyc –60 Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × ns tcyc –50 Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × ns tcyc –60 Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
PAGE 829
Section 25 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 25.34 shows the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 25.34 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.
PAGE 830
Section 25 Electrical Characteristics Condition A Condition B 20 MHz Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 25.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 25.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 25.
PAGE 831
Section 25 Electrical Characteristics 25.4.4 A/D Conversion Characteristics Tables 25.35 and 25.36 list the A/D conversion characteristics. Table 25.35 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 832
Section 25 Electrical Characteristics Table 25.36 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 833
Section 25 Electrical Characteristics 25.4.5 D/A Conversion Characteristics Table 25.37 lists the D/A conversion characteristics. Table 25.37 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 834
Section 25 Electrical Characteristics 25.4.6 Flash Memory Characteristics Table 25.38 shows the flash memory characteristics. Table 25.38 Flash Memory Characteristics Conditions (5-V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications) (3-V version): VCC = 3.0 V to 3.
PAGE 835
Section 25 Electrical Characteristics 3. Block erase time (shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = wait time after P-bit setting (z) × maximum programming count (N)) 5. Number of times when the wait time after P-bit setting (z) = 200 µs. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP (max)). 6.
PAGE 836
Section 25 Electrical Characteristics 25.5 Electrical Characteristics of H8S/2134 F-ZTAT (A-Mask Version), and Mask ROM Versions of H8S/2134 and H8S/2133 25.5.1 Absolute Maximum Ratings Table 25.39 lists the absolute maximum ratings. Table 25.39 Absolute Maximum Ratings Item Symbol Value Unit 1 Power supply voltage* 1 Power supply voltage* (3-V version) VCC –0.3 to +7.0 V VCC –0.3 to +4.3 V Powr supply voltage* (VCL pin) VCL –0.3 to +4.3 V Input voltage (except ports 6 and 7) Vin –0.
PAGE 837
Section 25 Electrical Characteristics 25.5.2 DC Characteristics Table 25.40 lists the DC characteristics. Table 25.41 lists the permissible output currents. Table 25.40 DC Characteristics (1) 1 1 Conditions: VCC = 5.0 V ±10%, AVCC* = 5.0 V ±10%, VSS = AVSS* = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol – Min Typ Max Test Unit Conditions 1.0 — — V — — VCC × 0.
PAGE 838
Section 25 Electrical Characteristics Item Input pull-up MOS current Ports 1 to 3 Min Typ Max Test Unit Conditions –IP 30 — 300 µA 60 — 600 µA — — 80 pF Port 6 Input RES capacitance NMI (4) Cin Vin = 0 V, VCC = 5 V ±10% Vin = 0 V, f = 1 MHz, Ta = 25°C — — 50 pF P52, P97, P42, P86 — — 20 pF Input pins except (4) above — — 15 pF — 55 70 mA f = 20 MHz — 36 55 mA f = 20 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 3.2 7.0 mA — 0.01 5.
PAGE 839
Section 25 Electrical Characteristics Table 25.40 DC Characteristics (2) 1 1 Conditions: VCC = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Symbol 2 4 P67 to P60* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 (1) – VT + VT + – VT – VT – VT + VT + Input high voltage Input low voltage Typ Max Test Unit Conditions 1.0 — — V — — VCC × 0.7 V 0.4 — — V 0.
PAGE 840
Section 25 Electrical Characteristics Item Symbol Min Typ Max Test Unit Conditions Three-state Ports 1 to 6, 8, 9 leakage current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.5 V Input pull-up MOS current –IP 30 — 300 µA Port 6 60 — 600 µA Vin = 0 V, VCC = 4.5 V to 5.
PAGE 841
Section 25 Electrical Characteristics Table 25.40 DC Characteristics (3) 5 1 1 Conditions: VCC = 2.7 V to 3.6 V* , AVCC* = 2.7 V to 3.6 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Schmitt trigger input voltage Input high voltage Input low voltage Symbol 2 4 P67 to P60* * , (1) 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 – VT + VT Min Typ Max Test Unit Conditions VCC × 0.2 — — V — — VCC × 0.7 V VT – VT VCC × 0.05 — — V VIH VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.
PAGE 842
Section 25 Electrical Characteristics Item Input pull-up MOS current Ports 1 to 3 Min Typ Max Test Unit Conditions –IP 5 — 150 µA 30 — 300 µA — — 80 pF Port 6 Input RES capacitance NMI (4) Cin Vin = 0 V, VCC = 2.7 V to 3.6 V Vin = 0 V, f = 1 MHz, Ta = 25°C — — 50 pF P52, P97, P42, P86 — — 20 pF Input pins except (4) above — — 15 pF — 30 40 mA f = 10 MHz — 20 32 mA f = 10 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 3.2 7.0 mA — 0.01 5.
PAGE 843
Section 25 Electrical Characteristics Table 25.41 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
PAGE 844
Section 25 Electrical Characteristics (1) Clock Timing Table 25.42 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 25.42 Clock Timing Condition A: VCC = 5.
PAGE 845
Section 25 Electrical Characteristics (2) Control Signal Timing Table 25.43 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 25.43 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.
PAGE 846
Section 25 Electrical Characteristics (3) Bus Timing Table 25.44 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 25.44 Bus Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
PAGE 847
Section 25 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Unit Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × ns tcyc –60 Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × ns tcyc –50 Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × ns tcyc –60 Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.5 × tcyc –35 — 2.
PAGE 848
Section 25 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 25.45 shows the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 25.45 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.
PAGE 849
Section 25 Electrical Characteristics Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 25.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 25.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — Item TMR Condition A Figure 25.
PAGE 850
Section 25 Electrical Characteristics 25.5.4 A/D Conversion Characteristics Tables 25.46 and 25.47 list the A/D conversion characteristics. Table 25.46 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 851
Section 25 Electrical Characteristics Table 25.47 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 852
Section 25 Electrical Characteristics 25.5.5 D/A Conversion Characteristics Table 25.48 lists the D/A conversion characteristics. Table 25.48 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
PAGE 853
Section 25 Electrical Characteristics 25.5.6 Flash Memory Characteristics Table 25.49 shows the flash memory characteristics. Table 25.49 Flash Memory Characteristics (Programming/Erasing Operating Range) Conditions (5-V version): VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) (3-V version): VCC = 3.0 V to 3.
PAGE 854
Section 25 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4.
PAGE 855
Section 25 Electrical Characteristics 25.5.7 Usage Note (1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc.
PAGE 856
Section 25 Electrical Characteristics 25.6 Operational Timing This section shows timing diagrams. Figure 25.4 shows the test conditions for the AC characteristics. VCC RL C = 30 pF: All output ports RL = 2.4 kΩ RH = 12 kΩ Chip output pin I/O timing test levels • Low level: 0.8 V • High level: 2.0 V RH C Figure 25.4 Output Load Circuit 25.6.1 Clock Timing tcyc tCH tCf φ tCL tCr Figure 25.5 System Clock Timing Rev. 4.
PAGE 857
Section 25 Electrical Characteristics EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 25.6 Oscillation Settling Timing φ NMI IRQi (i=0, 1, 2, 6, 7) tOSC2 Figure 25.7 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 4.
PAGE 858
Section 25 Electrical Characteristics 25.6.2 Control Signal Timing φ tRESS tRESS RES tRESW Figure 25.8 Reset Input Timing φ tNMIH tNMIS NMI tNMIW IRQi (i = 7 to 0) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 25.9 Interrupt Input Timing Rev. 4.
PAGE 859
Section 25 Electrical Characteristics 25.6.3 Bus Timing T1 T2 φ tAD A15 to A0, IOS* tCSD tAS tAH tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D7 to D0 (read) tWRD2 WR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.10 Basic Bus Timing (Two-State Access) Rev. 4.
PAGE 860
Section 25 Electrical Characteristics T1 T2 T3 φ tAD A15 to A0, IOS* tCSD tAS tASD tAH tASD AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D7 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D7 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.11 Basic Bus Timing (Three-State Access) Rev. 4.
PAGE 861
Section 25 Electrical Characteristics T1 T2 TW T3 φ A15 to A0, IOS* AS* RD (read) D7 to D0 (read) WR (write) D7 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.12 Basic Bus Timing (Three-State Access with One Wait State) Rev. 4.
PAGE 862
Section 25 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A15 to A0, IOS* tAS tASD tAH tASD AS* tRSD2 RD (read) tACC3 tRDS D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.13 Burst ROM Access Timing (Two-State Access) Rev. 4.
PAGE 863
Section 25 Electrical Characteristics T1 T2 or T3 T1 φ tAD A15 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D7 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.14 Burst ROM Access Timing (One-State Access) 25.6.4 Timing of On-Chip Supporting Modules T1 T2 φ tPRS tPRH Ports 1 to 9 (read) tPWD Ports 1 to 6, 8, 9 (write) Figure 25.15 I/O Port Input/Output Timing Rev. 4.
PAGE 864
Section 25 Electrical Characteristics φ tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 25.16 FRT Input/Output Timing φ tFTCS FTCI tFTCWL tFTCWH Figure 25.17 FRT Clock Input Timing φ tTMOD TMO0, TMO1 TMOX Figure 25.18 8-Bit Timer Output Timing Rev. 4.
PAGE 865
Section 25 Electrical Characteristics φ tTMCS tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH Figure 25.19 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 25.20 8-Bit Timer Reset Input Timing φ tPWOD PW15 to PW0, PWX1 to PWX0 Figure 25.21 PWM, PWMX Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 25.22 SCK Clock Input Timing Rev. 4.
PAGE 866
Section 25 Electrical Characteristics SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 25.23 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 25.24 A/D Converter External Trigger Input Timing Rev. 4.
PAGE 867
Section 25 Electrical Characteristics Host interface read timing CS/HA0 tHAR tHRPW tHRA IOR tHRD HDB7 to HDB0 tHRF Valid data tHIRQ HIRQi* (i = 1, 11, 12) Note: * The rising edge timing is the same as the port 4 output timing. See figure 25.15. Host interface write timing CS/HA0 tHAW tHWPW tHWA IOW tHDW tHWD HDB7 to HDB0 tHGA GA20 Figure 25.25 Host Interface Timing Rev. 4.
PAGE 868
Section 25 Electrical Characteristics VIH SDA0, SDA1 VIL tBUF tSCLH tSTAH SCL0, SCL1 P* tSTAS S* tSf tSP tSTOS Sr* tSCLL tSr tSCL P* tSDAS tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 25.26 I C Bus Interface Input/Output Timing (Option) Rev. 4.
PAGE 869
Appendix A Instruction Set Appendix A Instruction Set A.
PAGE 870
Appendix A Instruction Set Condition Code Notation Symbol Meaning Changes according operation result. * Indeterminate (value not guaranteed). 0 Always cleared to 0. 1 Always set to 1. — Not affected by operation result. Rev. 4.
PAGE 871
Appendix A Instruction Set Table A.1 Instruction Set 1. Data Transfer Instructions B MOV.B @ERs+,Rd B MOV.B @aa:8,Rd B MOV.B @aa:16,Rd H N Z V C Advanced MOV.B @(d:32,ERs),Rd No. of States*1 Normal B I — MOV.B @(d:16,ERs),Rd @@aa B @(d,PC) MOV.B @ERs,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B MOV.B Rs,Rd @ERn MOV.
PAGE 872
Appendix A Instruction Set L MOV.L @ERs+,ERd L MOV.L @aa:16,ERd L MOV.L @aa:32,ERd L MOV.L ERs,@ERd L MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd L MOV.L ERs,@aa:16 L MOV.L ERs,@aa:32 L POP.W Rn W POP.L ERn H N Z V C Advanced MOV.L @(d:32,ERs),ERd No. of States*1 Normal L I — MOV.L @(d:16,ERs),ERd @@aa L @(d,PC) MOV.L @ERs,ERd Condition Code Operation @aa 6 L @-ERn/@ERn+ L MOV.L ERs,ERd @ERn #xx MOV.
PAGE 873
Appendix A Instruction Set 2. Arithmetic Instructions L ADD.L ERs,ERd L ADDX #xx:8,Rd B ADDX Rs,Rd B ADDS #1,ERd H N Z V C Advanced ADD.L #xx:32,ERd No. of States*1 Normal W I — ADD.W Rs,Rd @@aa W @(d,PC) ADD.W #xx:16,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B ADD.B Rs,Rd @ERn #xx ADD.
PAGE 874
Appendix A Instruction Set Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) DAS DAS Rd B 2 Rd8 decimal adjust →Rd8 — * * — 1 MULXU MULXU.B Rs,Rd B 2 Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — 12 MULXU.W Rs,ERd W 2 Rd16×Rs16→ERd32 (unsigned multiplication) — — — — — — 20 MULXS.
PAGE 875
Appendix A Instruction Set MAC MAC @ERn+,@ERm+ Condition Code No. of States*1 Cannot be used with the H8S/2138 Group and H8S/2134 Group. V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) [2] CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd Rev. 4.
PAGE 876
Appendix A Instruction Set 3. Logic Instructions OR XOR NOT L AND.L ERs,ERd L OR.B #xx:8,Rd B OR.B Rs,Rd B OR.W #xx:16,Rd W OR.W Rs,Rd W OR.L #xx:32,ERd L OR.L ERs,ERd L XOR.B #xx:8,Rd B XOR.B Rs,Rd B XOR.W #xx:16,Rd W XOR.W Rs,Rd W XOR.L #xx:32,ERd L XOR.L ERs,ERd L NOT.B Rd H N Z V C Advanced AND.L #xx:32,ERd No. of States*1 Normal W I — AND.W Rs,Rd @@aa W @(d,PC) AND.W #xx:16,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B AND.B Rs,Rd @ERn AND.
PAGE 877
Appendix A Instruction Set 4. Shift Instructions SHAL SHAR SHLL SHLR ROTXL Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) SHAL.B Rd B 2 — — 1 SHAL.B #2,Rd B 2 — — 1 SHAL.W Rd W 2 0 — — 1 SHAL.W #2,Rd W 2 — — 1 SHAL.L ERd L 2 — — 1 SHAL.L #2,ERd L 2 — — SHAR.B Rd B 2 — — 0 1 SHAR.B #2,Rd B 2 — — 0 1 SHAR.
PAGE 878
Appendix A Instruction Set ROTXR ROTL ROTR Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) ROTXR.B Rd B 2 — — 0 1 ROTXR.B #2,Rd B 2 — — 0 1 ROTXR.W Rd W 2 — — 0 1 ROTXR.W #2,Rd W 2 — — 0 1 ROTXR.L ERd L 2 — — 0 1 ROTXR.L #2,ERd L 2 — — 0 1 ROTL.B Rd B 2 — — 0 1 ROTL.B #2,Rd B 2 — — 0 1 ROTL.
PAGE 879
Appendix A Instruction Set 5. Bit Manipulation Instructions BSET BCLR BNOT Condition Code No.
PAGE 880
Appendix A Instruction Set BTST BLD BILD BST BIST Condition Code No.
PAGE 881
Appendix A Instruction Set BAND BIAND BOR BIOR BXOR BIXOR Condition Code No.
PAGE 882
Appendix A Instruction Set 6.
PAGE 883
Appendix A Instruction Set JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — Condition Code No.
PAGE 884
Appendix A Instruction Set 7. System Control Instructions Condition Code No.
PAGE 885
Appendix A Instruction Set STC ANDC ORC XORC NOP Condition Code No.
PAGE 886
Appendix A Instruction Set 8. Block Transfer Instructions No. of States*1 V C Normal H N Z — @@aa @(d,PC) I Advanced Condition Code Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) EEPMOV EEPMOV.B — 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; — — — — — — 4+2n*2 EEPMOV.W — 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; — — — — — — 4+2n*2 Notes: 1.
PAGE 887
Bcc BAND ANDC AND 6 rs 6 F 9 6 A 1 6 1 7 6 7 0 0 0 W L L B B AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR 1 3 E A A 0 8 1 8 7 6 6 4 5 4 5 B B B — — — — BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) 1 0 0 erd C 7 B BAND #xx:3,@ERd disp disp abs 0 IMM 6 7 IMM B rd rd rd 0 0 0 0 0 rd 1 0 0 erd IMM rd 0 erd 0 erd 0 erd IMM BAND #xx:3,Rd 4 rs 6 1 B W AND.
PAGE 888
Bcc Instruction — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Size BHI d:8 Mnemonic Rev. 4.
PAGE 889
BIOR BILD BIAND BCLR Instruction B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Size BCLR #xx:3,Rd Mnemonic 6
PAGE 890
Rev. 4.
PAGE 891
BTST BST BSR BSET BOR Instruction 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTS
PAGE 892
6 6 7 7 7 6 6 B B B B B B B BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 Rev. 4.00 Jun 06, 2006 page 836 of 1004 REJ09B0301-0400 5 5 7 7 B — — EEPMOV EEPMOV.B EEPMOV.W L DEC.L #1,ERd W 1 W DEC.W #2,Rd DIVXU.W Rs,ERd 1 W DEC.W #1,Rd DIVXU.B Rs,Rd 1 B DEC.B Rd DEC 0 1 B DAS Rd DAS W 1 B DAA Rd DAA DIVXS.W Rs,ERd 0 L CMP.L ERs,ERd 0 1 L CMP.L #xx:32,ERd 1 7 W CMP.W Rs,Rd L 1 W CMP.
PAGE 893
LDC JSR JMP INC EXTU EXTS Instruction W W W W W W W LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR B LDC Rs,CCR W B LDC #xx:8,EXR LDC @(d:16,ERs),CCR B LDC #xx:8,CCR W — JSR @@aa:8 LDC @ERs,EXR — JSR @aa:24 B — JSR @ERn W — JMP @@aa:8 LDC @ERs,CCR — JMP @aa:24 LDC Rs,EXR L INC.L #1,ERd — L INC.W #2,Rd JMP @ERn W INC.W #1,Rd INC.L #2,ERd B W INC.B Rd L EXTU.L ERd L W EXTS.L ERd EXTU.
PAGE 894
B B B B B B B B B B B B B B B B W W W W W MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV L — LDMAC ERs,MACL MAC @ERn+,@ERm+ L L LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH L LDM.
PAGE 895
0 ers 0 erd 0 erd 0 erd 0 ers 0 2 D B B 7 6 6 6 0 erd 0 0 0 0 0 0 0 0 0 0 0 0 0 B A F 1 1 1 1 1 1 6 7 0 0 0 0 0 0 0 1 erd 0 ers 0 erd 1 erd 0 ers 8 A F 8 D B B 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 L L L L L L L L L MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L 1 MOV.L ERs,@(d:32,ERd)* L L MOV.L @ERs,ERd MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.
PAGE 896
Rev. 4.00 Jun 06, 2006 page 840 of 1004 REJ09B0301-0400 6 7 0 0 0 6 W L L B B W OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn ROTL PUSH POP ORC 1 1 1 1 1 B W W L L ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 ROTL.B Rd ROTL.B #2, Rd 0 L B PUSH.L ERn 6 7 W OR.W #xx:16,Rd 0 1 B OR.B Rs,Rd L C B OR.B #xx:8,Rd W 1 L NOT.L ERd PUSH.W Rn 1 W NOT.W Rd POP.L ERn 1 B NOT.B Rd OR 0 — NOP 1 L NEG.L ERd NOT 1 W NEG.
PAGE 897
rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 B W W L L SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd 1 5 — B 5 SHAL.B Rd 1 L — ROTXR.L #2, ERd SHAL 1 L ROTXR.L ERd RTS 1 W ROTXR.W #2, Rd RTS 1 W ROTXR.W Rd RTE 1 B ROTXR.B #2, Rd ROTXL.L #2, ERd 1 1 L ROTXL.L ERd 1 1 W ROTXL.
PAGE 898
Rev. 4.00 Jun 06, 2006 page 842 of 1004 REJ09B0301-0400 6 6 6 6 7 7 6 6 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 B W W STC.W EXR,@ERd STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W STC.W CCR,@ERd STC.W CCR,@(d:16,ERd) W W STC.B EXR,Rd STC.W CCR,@-ERd STC.
PAGE 899
1 7 1 7 1 1 1 1 B 1 0 5 D 1 7 6 7 0 W W L L L L L B B B — B B W W L L SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*2 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.
PAGE 900
B B XORC #xx:8,EXR Size XORC #xx:8,CCR Mnemonic 0 0 1 5 1st byte 4 IMM 1 2nd byte 0 5 3rd byte IMM 4th byte 7th byte 8th byte 9th byte 10th byte Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits, indicating an 8-bit or 16-bit register. rs, rd, and rn correspond to operand formats Rs, Rd, and Rn, respectively.) Register field (3 bits, indicating an address register or 32-bit register.
PAGE 901
1 2 BH 3 BL BHI BLS XOR BSR BCS AND RTE BNE BST TRAPA BEQ SUB ADD ADD MOV OR XOR AND MOV D E F SUBX B BVS 9 Table A.3 (2) MOV Table A.3 (2) C Note: * Cannot be used with the H8S/2138 Group and H8S/2134 Group. 8 BVC MOV.B Table A.3 (2) LDC 7 BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND OR RTS BCC AND ANDC 6 CMP BTST DIVXU XOR XORC 5 ADDX BCLR MULXU OR ORC 4 B BMI Table A.3 (2) Table A.3 (2) Table A.3 (2) Table A.3 (2) EEPMOV JMP BPL Table A.
PAGE 902
Rev. 4.00 Jun 06, 2006 page 846 of 1004 REJ09B0301-0400 ROTXR 13 MOV MOV MOV 79 7A ADD CMP CMP MOV ADD BHI BRN 2 BH Table A.3 (4) AL SUB SUB Table A.3 (4) BLS NOT STM 3 BL 2nd byte OR OR * MOVFPE BCC ROTXR ROTXL SHLR SHLL STC 4 LDC XOR XOR BCS DEC EXTU INC 5 Note: * Cannot be used with the H8S/2138 Group and H8S/2134 Group.
PAGE 903
BCLR MULXS 2 DIVXS 3 BSET 7Faa7*2 BNOT BNOT BCLR BCLR Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
PAGE 904
Rev. 4.00 Jun 06, 2006 page 848 of 1004 REJ09B0301-0400 AH BSET 0 BNOT BNOT 1 AL 1st byte BSET 1 0 BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Note: * aa is the absolute address specification.
PAGE 905
Appendix A Instruction Set A.4 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8S/2000 CPU. Table A.5 shows the number of instruction fetch, data read/write, and other cycles occurring in each instruction, and table A.4 shows the number of states required per cycle according to the bus size.
PAGE 906
Appendix A Instruction Set Table A.
PAGE 907
Appendix A Instruction Set Table A.5 Number of Cycles per Instruction Instruction Mnemonic ADD Instruction Fetch I ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND.B #xx:8,Rd 1 AND.B Rs,Rd 1 AND ANDC BAND Bcc AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.L #xx:32,ERd 3 Branch Address Read J Stack Operation K Byte Data Access L AND.
PAGE 908
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic Bcc BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 Byte Data Access L Word Data Access M Internal Operation N 2 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 2 1 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BIAND Stack Operation K BRA d:16 BHI d:16 BCLR Branch Address Read J 2 1 2 1 2 1 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE d:16 2 1 BLT d:16 2 1 BGT
PAGE 909
Appendix A Instruction Set Instruction Mnemonic Instruction Fetch I BILD 1 BIOR BIST BIXOR BLD BNOT BILD #xx:3,Rd Branch Address Read J Stack Operation K Byte Data Access L BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4 1 BIOR #xx:8,Rd 1 BIOR #xx:8,@ERd 2 1 BIOR #xx:8,@aa:8 2 1 BIOR #xx:8,@aa:16 3 1 BIOR #xx:8,@aa:32 4 1 BIST #xx:3,Rd 1 BIST #xx:3,@ERd 2 2 BIST #xx:3,@aa:8 2 2 BIST #xx:3,@aa:16 3 2 BIST #xx:3,@aa:32 4 2
PAGE 910
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic BOR BSET BSR BTST Stack Operation K Byte Data Access L BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 1 BOR #xx:3,@aa:8 2 1 BOR #xx:3,@aa:16 3 1 BOR #xx:3,@aa:32 4 1 BSET #xx:3,Rd 1 BSET #xx:3,@ERd 2 2 BSET #xx:3,@aa:8 2 2 BSET #xx:3,@aa:16 3 2 BSET #xx:3,@aa:32 4 2 BSET Rn,Rd 1 BSET Rn,@ERd 2 2 BSET Rn,@aa:8 2 2 BSET Rn,@aa:16 3 2 BSET Rn,@aa:32 4 2 BSR d:8 BSR d:16 BST Branch Address Read J Word Data
PAGE 911
Appendix A Instruction Set Instruction Mnemonic Instruction Fetch I BXOR 1 BXOR #xx:3,Rd Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 BXOR #xx:3,@aa:32 4 1 CLRMAC CLRMAC Cannot be used with the H8S/2138 Group and H8S/2134 Group. CMP CMP.B #xx:8,Rd 1 CMP.B Rs,Rd 1 CMP.W #xx:16,Rd 2 CMP.W Rs,Rd 1 CMP.L #xx:32,ERd 3 CMP.L ERs,ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC.
PAGE 912
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic JSR LDC 4 LDM* LDMAC JSR @ERn Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Normal 2 1 Advanced 2 2 JSR @aa:24 Normal 2 1 1 Advanced 2 2 1 JSR @@aa:8 Normal 2 1 1 Advanced 2 2 2 LDC #xx:8,CCR 1 LDC #xx:8,EXR 2 LDC Rs,CCR 1 LDC Rs,EXR 1 LDC @ERs,CCR 2 LDC @ERs,EXR 2 1 LDC @(d:16,ERs),CCR 3 1 LDC @(d:16,ERs),EXR 3 1 LDC @(d:32,ERs),CCR
PAGE 913
Appendix A Instruction Set Instruction Mnemonic Instruction Fetch I MOV Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M MOV.B @aa:32,Rd 3 MOV.B Rs,@ERd 1 1 MOV.B Rs,@(d:16,ERd) 2 1 MOV.B Rs,@(d:32,ERd) 4 1 MOV.B Rs,@-ERd 1 1 MOV.B Rs,@aa:8 1 1 MOV.B Rs,@aa:16 2 1 MOV.B Rs,@aa:32 3 1 MOV.W #xx:16,Rd 2 MOV.W Rs,Rd 1 MOV.W @ERs,Rd 1 1 MOV.W @(d:16,ERs),Rd 2 1 MOV.W @(d:32,ERs),Rd 4 1 MOV.W @ERs+,Rd 1 1 MOV.
PAGE 914
Appendix A Instruction Set Branch Address Read J Instruction Mnemonic Instruction Fetch I Cannot be used with the H8S/2138 Group and H8S/2134 Group. MOVFPE MOVFPE @:aa:16,Rd MOVTPE MOVTPE Rs,@:aa:16 MULXS MULXS.B Rs,Rd MULXU NEG 2 19 11 MULXU.W Rs,ERd 1 19 NEG.B Rd 1 NEG.W Rd 1 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 ROTL 11 1 1 PUSH Internal Operation N MULXU.B Rs,Rd NOP POP Word Data Access M MULXS.W Rs,ERd NOP ORC Byte Data Access L 2 NEG.
PAGE 915
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic ROTR ROTXL ROTXR ROTR.B Rd 1 ROTR.B #2,Rd 1 ROTR.W Rd 1 ROTR.W #2,Rd 1 ROTR.L ERd 1 ROTR.L #2,ERd 1 ROTXL.B Rd 1 ROTXL.B #2,Rd 1 ROTXL.W Rd 1 ROTXL.W #2,Rd 1 ROTXL.L ERd 1 ROTXL.L #2,ERd 1 ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 ROTXR.L ERd 1 ROTXR.
PAGE 916
Appendix A Instruction Set Instruction Mnemonic SHLL SHLR Instruction Fetch I SHLL.B Rd 1 SHLL.B #2,Rd 1 SHLL.W Rd 1 SHLL.W #2,Rd 1 SHLL.L ERd 1 SHLL.L #2,ERd 1 SHLR.B Rd 1 SHLR.B #2,Rd 1 SHLR.W Rd 1 SHLR.W #2,Rd 1 SHLR.L ERd 1 SHLR.L #2,ERd 1 SLEEP SLEEP 1 STC STC.B CCR,Rd 1 STC.B EXR,Rd 1 4 STM* SUB Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 STC.W CCR,@ERd 2 1 STC.W EXR,@ERd 2 1 STC.
PAGE 917
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic SUBS SUBS #1/2/4,ERd 1 SUBX SUBX #xx:8,Rd 1 SUBX Rs,Rd 1 TAS 3 TAS @ERd* TRAPA TRAPA #x:2 XOR XORC Notes: 1. 2. 3. 4. Branch Address Read J Stack Operation K 2 Byte Data Access L Word Data Access M Internal Operation N 2 Normal 2 1 1 2/3* 2 Advanced 2 2 1 2/3* 2 XOR.B #xx:8,Rd 1 XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.
PAGE 918
Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle.
PAGE 919
Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD and WR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD WR High level R:W 2nd Internal operation Fetching 3rd byte Fetching 4th byte of instruction of instruction R:W EA Fetching 1st byte Fetching 2nd byte of branch of branch instruction instruction Figure A.
PAGE 920
Appendix A Instruction Set Table A.6 Instruction Execution Cycle Instruction ADD.B #xx:8,Rd 1 2 3 4 5 R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT AND.B #xx:8,Rd R:W NEXT AND.B Rs,Rd R:W NEXT AND.W #xx:16,Rd R:W 2nd AND.W Rs,Rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT AND.L #xx:32,ERd R:W 2nd R:W 3rd AND.
PAGE 921
Appendix A Instruction Set Instruction 1 2 BMI d:8 R:W NEXT R:W EA BGE d:8 R:W NEXT R:W EA BLT d:8 R:W NEXT R:W EA BGT d:8 R:W NEXT R:W EA BLE d:8 R:W NEXT R:W EA 3 BRA d:16 (BT d:16) R:W 2nd Internal R:W EA operation, 1 state BRN d:16 (BF d:16) R:W 2nd Internal R:W EA operation, 1 state BHI d:16 R:W 2nd Internal R:W EA operation, 1 state BLS d:16 R:W 2nd Internal R:W EA operation, 1 state BCC d:16 (BHS d:16) R:W 2nd Internal R:W EA operation, 1 state BCS d:16 (BLO d:16) R:W 2nd
PAGE 922
Appendix A Instruction Set Instruction 1 2 3 BLT d:16 R:W 2nd Internal R:W EA operation, 1 state BGT d:16 R:W 2nd Internal R:W EA operation, 1 state BLE d:16 R:W 2nd Internal R:W EA operation, 1 state BCLR #xx:3,Rd R:W NEXT 4 BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3, @aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BCLR #xx:3, @aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W
PAGE 923
Appendix A Instruction Set Instruction 1 BILD #xx:3,@aa:32 R:W 2nd 2 3 4 R:W 3rd R:W 4th BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BIOR #xx:3,Rd R:B EA 6 7 8 9 R:W NEXT BIST #xx:3,Rd R:W NEXT BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:16 R:W 2nd R:W 3rd
PAGE 924
Appendix A Instruction Set Instruction 1 2 3 4 BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT BNOT #xx:3, @aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BNOT #xx:3, @aa:32 R:W 2nd R:W 3rd R:W 4th 6 W:B EA R:B:M EA R:W:M NEXT BNOT Rn,Rd R:W NEXT BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th BOR #xx:3,Rd R:W NEXT BOR #xx:3,@ERd R:W 2nd R
PAGE 925
Appendix A Instruction Set Instruction 1 2 BSR d:8 Advanced R:W NEXT R:W EA BSR d:16 Advanced R:W 2nd 3 W:W:M Stack (H) 4 Internal R:W EA operation, 1 state W:W:M Stack (H) BST #xx:3,Rd R:W NEXT BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BTST
PAGE 926
Appendix A Instruction Set Instruction 1 CMP.B #xx:8,Rd R:W NEXT CMP.B Rs,Rd R:W NEXT CMP.W #xx:16,Rd R:W 2nd CMP.W Rs,Rd R:W NEXT CMP.L #xx:32,ERd R:W 2nd CMP.L ERs,ERd R:W NEXT DAA Rd R:W NEXT DAS Rd R:W NEXT DEC.B Rd R:W NEXT DEC.W #1/2,Rd R:W NEXT 2 3 4 5 6 R:W NEXT R:W 3rd R:W NEXT DEC.L #1/2,ERd R:W NEXT DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states DIVXU.
PAGE 927
Appendix A Instruction Set Instruction 1 LDC #xx:8,CCR R:W NEXT LDC #xx:8,EXR R:W 2nd LDC Rs,CCR R:W NEXT 2 3 4 5 6 7 8 9 R:W NEXT LDC Rs,EXR R:W NEXT LDC @ERs,CCR R:W 2nd LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA LDC@(d:16,ERs), CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC@(d:16,ERs), EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC@(d:32,ERs), CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LDC@(d:32,ERs), EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LDC @ERs+,CCR R:W
PAGE 928
Appendix A Instruction Set Instruction MOV.B @(d:32,ERs),Rd 1 R:W 2nd 2 R:W 3rd 3 R:W 4th 4 5 R:W NEXT R:B EA MOV.B @ERs+,Rd R:W NEXT Internal R:B EA operation, 1 state MOV.B @aa:8,Rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA MOV.B Rs,@ERd R:W NEXT W:B EA MOV.B Rs, @(d:16,ERd) R:W 2nd R:W NEXT W:B EA MOV.B Rs, @(d:32,ERd) R:W 2nd R:W 3rd MOV.B Rs,@-ERd R:W NEXT Internal W:B EA operation, 1 state MOV.
PAGE 929
Appendix A Instruction Set Instruction 1 MOV.L #xx:32,ERd R:W 2nd 2 3 4 5 R:W 3rd R:W NEXT MOV.L @ERs,ERd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2 MOV.L @(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th MOV.L @ERs+, ERd R:W 2nd R:W:M NEXT MOV.L @aa:16, ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @aa:32, ERd R:W 2nd R:W:M 3rd R:W 4th MOV.
PAGE 930
Appendix A Instruction Set Instruction 1 NOT.L ERd R:W NEXT OR.B #xx:8,Rd R:W NEXT OR.B Rs,Rd R:W NEXT OR.W #xx:16,Rd R:W 2nd OR.W Rs,Rd R:W NEXT 2 3 R:W 2nd R:W 3rd OR.L ERs,ERd R:W 2nd R:W NEXT R:W NEXT ORC #xx:8,CCR R:W NEXT ORC #xx:8,EXR R:W 2nd POP.W Rn R:W NEXT Internal R:W EA operation, 1 state POP.L ERn R:W 2nd PUSH.W Rn R:W NEXT Internal W:W EA operation, 1 state PUSH.L ERn R:W 2nd R:W NEXT ROTL.B #2,Rd R:W NEXT ROTL.W Rd R:W NEXT ROTL.W #2,Rd R:W NEXT ROTL.
PAGE 931
Appendix A Instruction Set Instruction 1 ROTXL.L #2,ERd R:W NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd R:W NEXT ROTXR.W Rd R:W NEXT ROTXR.W #2,Rd R:W NEXT ROTXR.L ERd R:W NEXT 2 ROTXR.L #2,ERd R:W NEXT RTE R:W NEXT R:W Stack (EXR) RTS Advanced R:W NEXT R:W:M Stack (H) SHAL.B Rd R:W NEXT SHAL.B #2,Rd R:W NEXT SHAL.W Rd R:W NEXT SHAL.W #2,Rd R:W NEXT SHAL.L ERd R:W NEXT SHAL.L #2,ERd R:W NEXT SHAR.B Rd R:W NEXT SHAR.B #2,Rd R:W NEXT SHAR.W Rd R:W NEXT SHAR.
PAGE 932
Appendix A Instruction Set Instruction SLEEP 1 2 3 4 5 6 R:W NEXT Internal operation :M STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC EXR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR, @(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC EXR, @(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC EXR, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR,@-ERd R:W 2nd R:W
PAGE 933
Appendix A Instruction Set Instruction 1 SUBS #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd R:W NEXT TAS @ERd*5 R:W 2nd 2 3 R:W NEXT XOR.B Rs,Rd R:W NEXT XOR.W #xx:16,Rd R:W 2nd XOR.W Rs,Rd R:W NEXT 5 6 7 8 9 W:W Stack (EXR) R:W:M VEC R:W VEC+2 Internal R:W* operation, 1 state W:W Stack (EXR) R:W:M VEC R:W VEC+2 Internal R:W *8 operation, 1 state R:W NEXT R:B:M EA W:B EA TRAPA Advanced R:W NEXT Internal W:W #x:2 operation, Stack (L) 1 state XOR.
PAGE 934
Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.
PAGE 935
Appendix B Internal I/O Registers Register Address Name H'FF82 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width PCSR — — — — — PWCKB PWCKA — PWM 8 EBR1 — — — — — — EB9/— EB8/— FLASH 8 SYSCR2 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E HIF 8 EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FLASH 8 H'FF84 SBYCR SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 SYSTEM 8 H'FF85 LPWRCR DTON LSON NESEL EXCLE — — — — H'FF86 MSTPCRH MSTP15 MSTP14
PAGE 936
Appendix B Internal I/O Registers Register Address Name H'FF9B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRBL Module Name Bus Width FRT 16 8 OCRAFL H'FF9C ICRCH OCRDMH 0 H'FF9D 0 0 0 0 0 0 0 ICRCL OCRDML H'FF9E ICRDH H'FF9F ICRDL H'FFA0 SMR2 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI2 DADRAH DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 PWMX DACR TEST PWME — — OEB OEA OS CKS DADRAL DA5 DA4 DA3 DA2 DA1 DA0 CFS — PWMX H'FFA2 SCR2 TIE RIE TE RE
PAGE 937
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 H'FFB8 P5DDR — — — — — P52DDR P51DDR P50DDR Ports H'FFB9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Bit 1 Bit 0 H'FFBA P5DR — — — — — P52DR P51DR P50DR H'FFBB P6DR P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR H'FFBD P8DDR — P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR H'FFBE P7PIN P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN H'FFBF
PAGE 938
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width H'FFDA SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI0 8 TDRE RDRF ORER FER PER TEND MPB MPBT SMIF H'FFDB TDR0 H'FFDC SSR0 H'FFDD RDR0 H'FFDE SCMR0 — — — — SDIR SINV — ICDR0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 SARX0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 H'FFDF ICMR0 I
PAGE 939
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF5 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 ODR1 TCORC Module Name Bus Width HIF 8 TMRX TISR — — — — — — — IS TMRY H'FFF6 STR1 DBU DBU DBU DBU C/D DBU IBF OBF HIF H'FFF7 TCORBX H'FFF8 DADR0 H'FFF9 DADR1 H'FFFA DACR TCORAX H'FFFC IDR2 TCONRI H'FFFD ODR2 TMRX D/A DAOE1 DAOE0 DAE — — — — IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF IC
PAGE 940
Appendix B Internal I/O Registers B.
PAGE 941
Appendix B Internal I/O Registers Lower Address H'FF88 H'FF89 Register Name H8S/2138 Group Register Selection Conditions H8S/2134 Group Register Selection Conditions Module Name SMR1 MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR ICCR1 MSTP3 = 0, IICE = 1 in STCR — SCI1 IIC1 BRR1 MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR SCI1 ICSR1 MSTP3 = 0, IICE = 1 in STCR — IIC1 H'FF8A SCR1 MSTP6 = 0 MSTP6 = 0 SCI1 H'FF8B TDR1 H'FF8C SSR1 MSTP6 = 0, IICE = 0 in STCR
PAGE 942
Appendix B Internal I/O Registers Lower Address H'FF9B H'FF9C H'FF9D H'FF9E Register Name ICRBL H8S/2138 Group Register Selection Conditions MSTP13 = 0 H8S/2134 Group Register Selection Conditions Module Name ICRS = 0 in MSTP13 = 0 TOCR ICRS = 0 in FRT TOCR OCRAFL ICRS = 1 in TOCR ICRS = 1 in TOCR ICRCH ICRS = 0 in TOCR ICRS = 0 in TOCR OCRDMH ICRS = 1 in TOCR ICRS = 1 in TOCR ICRCL ICRS = 0 in TOCR ICRS = 0 in TOCR OCRDML ICRS = 1 in TOCR ICRS = 1 in TOCR ICRDH H'FF9F ICRDL H'FF
PAGE 943
Appendix B Internal I/O Registers Lower Address Register Name H'FFAC P1PCR H'FFAD P2PCR H'FFAE P3PCR H'FFB0 P1DDR H'FFB1 P2DDR H'FFB2 P1DR H'FFB3 P2DR H'FFB4 P3DDR H'FFB5 P4DDR H'FFB6 P3DR H'FFB7 P4DR H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBD P8DDR H'FFBE P7PIN H'FFBF P8DR H'FFC0 P9DDR H8S/2138 Group Register Selection Conditions H8S/2134 Group Register Selection Conditions Module Name No conditions No conditions Ports H'FFC1 P9DR H'FFC2 IER N
PAGE 944
Appendix B Internal I/O Registers Lower Address Register Name H'FFD2 PWOERB H'FFD3 PWOERA H'FFD4 PWDPRB H'FFD5 PWDPRA H8S/2138 Group Register Selection Conditions No conditions H8S/2134 Group Register Selection Conditions Module Name — PWM SCI0 H'FFD6 PWSL H'FFD7 PWDR0 to PWDR15 H'FFD8 SMR0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR ICCR0 MSTP4 = 0, IICE = 1 in STCR — IIC0 BRR0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR SCI0 H'FFD9 MSTP11 = 0 ICSR0
PAGE 945
Appendix B Internal I/O Registers Lower Address H'FFF0 Register Name H8S/2138 Group Register Selection Conditions HICR MSTP2 = 0, HIE = 1 in SYSCR TCRX MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TCRY H'FFF1 MSTP2 = 0, HIE = 1 in SYSCR TCSRX MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 — in TCONRS MSTP2 = 0, HIE = 1 in SYSCR TICRR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 — in TCONRS MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 — in TCONRS MSTP2 = 0, HIE = 1 in SYSCR TCORC MSTP8 = 0, HIE = 0 in SYSCR
PAGE 946
Appendix B Internal I/O Registers Lower Address H'FFFC H'FFFD H'FFFE H'FFFF Register Name H8S/2138 Group Register Selection Conditions H8S/2134 Group Register Selection Conditions Module Name IDR2 MSTP2 = 0, HIE = 1 in SYSCR TCONRI MSTP8 = 0, HIE = 0 in SYSCR Timer connection ODR2 MSTP2 = 0, HIE = 1 in SYSCR HIF TCONRO MSTP8 = 0, HIE = 0 in SYSCR Timer connection STR2 MSTP2 = 0, HIE = 1 in SYSCR TCONRS MSTP8 = 0, HIE = 0 in SYSCR SEDGR Rev. 4.
PAGE 947
Appendix B Internal I/O Registers B.3 Functions Register acronym Register name Address to which the register is mapped DACR—D/A Control Register H'FFFA Name of on-chip supporting module D/A Converter Bit numbers Bit Initial bit values 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W — — — — — Names of the bits. Dashes (—) indicate reserved bits.
PAGE 948
Appendix B Internal I/O Registers MRA—DTC Mode Register A Bit Initial value Read/Write H'EC00–H'EFFF DTC 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — — — DTC data transfer size 0 Byte-size transfer 1 Word-size transfer DTC transfer mode select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC mode 0 0 Normal mode 1 Repeat mode 1 0 Block tra
PAGE 949
Appendix B Internal I/O Registers MRB—DTC Mode Register B DTC 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Bit Initial value H'EC00–H'EFFF Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — DTC interrupt select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC chain transfer enable 0 End of DTC data transfer 1 DTC chain tra
PAGE 950
Appendix B Internal I/O Registers CRA—DTC Transfer Count Register A Bit Initial value Read/Write 15 14 13 12 11 10 H'EC00–H'EFFF 9 8 7 6 5 4 DTC 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — CRAH — — — — — CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B Bit Initial
PAGE 951
Appendix B Internal I/O Registers KBCOMP—Keyboard Comparator Control Register H'FEE4 IrDA/Expansion A/D 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Keyboard comparator control Bit 3 Bit 2 Bit 1 Bit 0 A/D converter A/D converter KBADE KBCH2 KBCH1 KBCH0 channel 6 input channel 7 input 0 — — — AN6 AN7 1 0 0 0 CIN0 Undefined 1 CIN1 0 CIN2 1 CIN3 0 CIN4 1 C
PAGE 952
Appendix B Internal I/O Registers DDCSWR—DDC Switch Register Bit Initial value Read/Write H'FEE6 IIC0 7 6 5 4 3 2 1 0 SWE SW IE IF CLR3 CLR2 CLR1 CLR0 0 0 0 0 1 1 1 1 R/W R/(W)*1 W*2 W*2 W*2 W*2 R/W R/W IIC clear bits Bit 3 Bit 2 Bit 1 Bit 0 Description CLR3 CLR2 CLR1 CLR0 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 0 IIC1 internal latch cleared 1 IIC0 and IIC1 internal latches cleared — Invalid setting 1 1 — — D
PAGE 953
Appendix B Internal I/O Registers ICRA—Interrupt Control Register A ICRB—Interrupt Control Register B ICRC—Interrupt Control Register C Bit H'FEE8 H'FEE9 H'FEEA Interrupt Controller Interrupt Controller Interrupt Controller 7 6 5 4 3 2 1 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Interrupt control level 0 Corresponding interrupt source is control level 0 (non-priority) 1 Corresponding interrupt s
PAGE 954
Appendix B Internal I/O Registers ISR—IRQ Status Register H'FEEB Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* IRQ7 to IRQ0 flags 0 [Clearing conditions] • Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF • When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn
PAGE 955
Appendix B Internal I/O Registers ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L H'FEEC H'FEED Interrupt Controller Interrupt Controller ISCRH Bit 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 1 0 IRQ7 to IRQ4 sense control A and B ISCRL Bit 7 6 5 4 3 2 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value 0
PAGE 956
Appendix B Internal I/O Registers DTCER—DTC Enable Register H'FEEE to H'FEF2 DTC 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit DTC activation enable 0 DTC activation by interrupt is disabled [Clearing conditions] • When data transfer ends with the DISEL bit set to 1 • When the specified number of transfers end 1 DTC activation by interrupt is enabled [Holding condition] Wh
PAGE 957
Appendix B Internal I/O Registers ABRKCR—Address Break Control Register H'FEF4 Interrupt Controller 7 6 5 4 3 2 1 0 CMF — — — — — — BIE Initial value 0 0 0 0 0 0 0 0 Read/Write R/W — — — — — — R/W Bit Break interrupt enable 0 Address break disabled 1 Address break enabled Condition match flag 0 [Clearing condition] When address break interrupt exception handling is executed 1 [Setting condition] When address set by BARA–BARC is prefetched while BIE = 1 Rev. 4.
PAGE 958
Appendix B Internal I/O Registers BARA—Break Address Register A BARB—Break Address Register B BARC—Break Address Register C Bit BARA H'FEF5 H'FEF6 H'FEF7 Interrupt Controller Interrupt Controller Interrupt Controller 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A19 A18 A17 A16 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Specifies address (bits 23 to 16) at which address break is to be generated 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A
PAGE 959
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'FF80 Flash Memory 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W Bit Program 0 Program mode cleared 1 Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 Erase 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 Program-verify 0 Program-verify mode cleared 1 Transit
PAGE 960
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'FF81 Flash Memory 7 6 5 4 3 2 1 0 FLER — — — — — ESU PSU Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — R/W R/W Bit Program setup 0 Program setup cleared 1 Program setup [Setting condition] When SWE = 1 Erase setup 0 Erase setup cleared 1 Erase setup [Setting condition] When SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (erro
PAGE 961
Appendix B Internal I/O Registers PCSR—Peripheral Clock Select Register H'FF82 PWM 7 6 5 4 3 — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — — R/W R/W — Bit 2 1 PWCKB PWCKA 0 — PWM clock select PWSL Bit 7 PCSR Bit 6 Bit 2 Bit 1 Description PWCKE PWCKS PWCKB PWCKA 0 — — — Clock input is disabled 1 0 — — φ (system clock) is selected 1 0 0 φ/2 is selected 1 φ/4 is selected 0 φ/8 is selected 1 φ/16 is selected 1 Rev. 4.
PAGE 962
Appendix B Internal I/O Registers SYSCR2—System Control Register 2 Bit H'FF83 HIF 7 6 5 4 3 2 1 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W Host interface enable 0 Host interface function disabled 1 Host interface function enabled CS3 enable 0 Host interface pin channel 3 functions disabled 1 Host interface pin channel 3 functions enabled CS4 enable 0 Host interface pin channel 4 functions dis
PAGE 963
Appendix B Internal I/O Registers EBR1—Erase Block Register 1 EBR2—Erase Block Register 2 Bit H'FF82 H'FF83 Flash Memory Flash Memory 7 6 5 4 3 2 1 0 2 * EB9/— EB8/—*2 — — — — — — Initial value 0 0 0 0 0 0 Read/Write — — — — — — Bit 7 6 5 4 3 2 1 0 0 0 1 2 R/W* * R/W*1 *2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W*1 R/W R/W R/W R/W R/W R/W R/W Notes: 1.
PAGE 964
Appendix B Internal I/O Registers SBYCR—Standby Control Register H'FF84 System 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W — R/W R/W R/W Bit System clock select 2 to 0 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock = φ/2 0 Medium-speed clock = φ/4 1 Medium-speed clock = φ/8 0 0 Medium-speed clock = φ/16 1 Medium-speed clock = φ/32 1 — — 1 1 Standby timer select 2 to 0 0 0 0 St
PAGE 965
Appendix B Internal I/O Registers LPWRCR—Low-Power Control Register H'FF85 System 7 6 5 4 3 2 1 0 DTON LSON NESEL EXCLE — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W — — — — Bit Subclock input enable 0 Subclock input from EXCL pin is disabled 1 Subclock input from EXCL pin is enabled Noise elimination sampling frequency select 0 Sampling at φ divided by 32 1 Sampling at φ divided by 4 Low-speed on flag 0 • When a SLEEP instruction is execute
PAGE 966
Appendix B Internal I/O Registers MSTPCRH—Module Stop Control Register H MSTPCRL—Module Stop Control Register L H'FF86 H'FF87 System System MSTPCRH 7 Bit 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module stop 0 Module stop mode is cleared 1 Module sto
PAGE 967
Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 SMR2—Serial Mode Register 2 SMR0—Serial Mode Register 0 Bit H'FF88 H'FFA0 H'FFD8 SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 1 and 0 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1
PAGE 968
Appendix B Internal I/O Registers 2 ICCR1—I C Bus Control Register 1 2 ICCR0—I C Bus Control Register 0 Bit H'FF88 H'FFD8 IIC1 IIC0 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/(W)* W Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1; writing is ignored I2C bus interface interrupt reques
PAGE 969
Appendix B Internal I/O Registers BRR1—Bit Rate Register 1 BRR2—Bit Rate Register 2 BRR0—Bit Rate Register 0 H'FF89 H'FFA1 H'FFD9 SCI1 SCI2 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transmit/receive bit rate Rev. 4.
PAGE 970
Appendix B Internal I/O Registers 2 ICSR1—I C Bus Status Register 1 2 ICSR0—I C Bus Status Register 0 Bit H'FF89 H'FFD9 IIC1 IIC0 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB Initial value 0 0 Read/Write R/(W)*1 0 0 0 0 0 1 1 1 1 1 * * * * * R/(W) R/(W) R/(W) R/(W) R/(W)*1 R/(W) 0 R/W Acknowledge bit 0 Receive mode: 0 is output at acknowledge output timing Transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is outp
PAGE 971
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 SCR2—Serial Control Register 2 SCR0—Serial Control Register 0 Bit H'FF8A H'FFA2 H'FFDA SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 1 and 0 0 0 1 1 0 1 Asynchronous mode Internal clock/SCK pin functions as I/O port Synchronous mode Internal clock/SCK pin functions as serial clock output Async
PAGE 972
Appendix B Internal I/O Registers RDR1—Receive Data Register 1 RDR2—Receive Data Register 2 RDR0—Receive Data Register 0 H'FF8D H'FFA5 H'FFDD SCI1 SCI2 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores serial receive data TDR1—Transmit Data Register 1 TDR2—Transmit Data Register 2 TDR0—Transmit Data Register 0 H'FF8B H'FFA3 H'FFDB SCI1 SCI2 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W
PAGE 973
Appendix B Internal I/O Registers SSR1—Serial Status Register 1 SSR2—Serial Status Register 2 SSR0—Serial Status Register 0 H'FF8C H'FFA4 H'FFDC SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Bit Multiprocessor bit transfer 0 Data with a 0 multi-processor bit is transmitted 1 Data with a 1 multi-processor bit is transmitted Multiprocessor bit 0 [Clearing condit
PAGE 974
Appendix B Internal I/O Registers SCMR1—Serial Interface Mode Register 1 SCMR2—Serial Interface Mode Register 2 SCMR0—Serial Interface Mode Register 0 Bit H'FF8E H'FFA6 H'FFDE SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value 1 1 1 1 0 0 1 0 Read/Write — — — — R/W R/W — R/W Serial communication interface mode select 0 Normal SCI mode 1 Setting prohibited Data invert 0 TDR contents are transmitted without modification Receive data is stored in RD
PAGE 975
Appendix B Internal I/O Registers 2 ICDR1—I C Bus Data Register 1 2 ICDR0—I C Bus Data Register 0 Bit H'FF8E H'FFDE IIC1 IIC0 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value — — — — — — — — Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 ICDRR Bit ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value — — — — — — — — Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 ICDRS Bit ICDRS7 ICD
PAGE 976
Appendix B Internal I/O Registers SARX1—Second Slave Address Register 1 SAR1—Slave Address Register 1 SARX0—Second Slave Address Register 0 SAR0—Slave Address Register 0 H'FF8E H'FF8F H'FFDE H'FFDF IIC1 IIC1 IIC0 IIC0 SAR Bit 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Slave address Format select SARX 7 6 5 4 3 2 1 0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Bit Ini
PAGE 977
Appendix B Internal I/O Registers 2 ICMR1—I C Bus Mode Register 1 2 ICMR0—I C Bus Mode Register 0 Bit H'FF8F H'FFDF IIC1 IIC0 7 6 5 4 3 2 1 0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit counter BC2 BC1 BC0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 Serial clock select IICX CKS2 0 0 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Synchronous serial format 8 1 2 3 4 5 6 7 I2C bus f
PAGE 978
Appendix B Internal I/O Registers TIER—Timer Interrupt Enable Register H'FF90 FRT 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W — Bit Timer overflow interrupt enable 0 Timer overflow interrupt request (FOVI) is disabled 1 Timer overflow interrupt request (FOVI) is enabled Output compare interrupt B enable 0 Output compare interrupt request B (OCIB) is disabled 1 Output compare inte
PAGE 979
Appendix B Internal I/O Registers TCSR—Timer Control/Status Register Bit H'FF91 FRT 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Counter clear A 0 1 FRC clearing is disabled FRC is cleared at compare match A Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When FRC changes from H'FFFF to H'0000 Output co
PAGE 980
Appendix B Internal I/O Registers FRC—Free-Running Counter H'FF92 FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA/OCRB—Output Compare Register A/B H'FF94 FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PAGE 981
Appendix B Internal I/O Registers TCR—Timer Control Register H'FF96 FRT 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Clock select 0 1 0 φ/2 internal clock source 1 φ/8 internal clock source 0 φ/32 internal clock source 1 External clock source (rising edge) Buffer enable B 0 ICRD is not used as a buffer register for input capture B 1 ICRD is used as a buffer registe
PAGE 982
Appendix B Internal I/O Registers TOCR—Timer Output Compare Control Register 7 Bit FRT 5 4 3 2 1 0 ICRS OCRS OEA OEB OLVLA OLVLB 6 ICRDMS OCRAMS H'FF97 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Output level B 0 A 0 logic level is output for compare-match B 1 A 1 logic level is output for compare-match B Output level A 0 A 0 logic level is output for compare-match A 1 A 1 logic level is output for compare-match A Output enable B 0 O
PAGE 983
Appendix B Internal I/O Registers OCRAR—Output Compare Register AR OCRAF—Output Compare Register AF H'FF98 H'FF9A FRT FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used for OCRA operation when OCRAMS = 1 in TOCR (For details, see section 11.2.4, Output Compare Registers AR and AF (OCRAR, OCRAF).
PAGE 984
Appendix B Internal I/O Registers DADRAH—PWM (D/A) Data Register AH DADRAL—PWM (D/A) Data Register AL DADRBH—PWM (D/A) Data Register BH DADRBL—PWM (D/A) Data Register BL H'FFA0 H'FFA1 H'FFA6 H'FFA7 PWMX PWMX PWMX PWMX DADRH DADRL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit (data) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — DADRA Initial value DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 — 1 Read/Write R
PAGE 985
Appendix B Internal I/O Registers DACR—PWM (D/A) Control Register H'FFA0 PWMX 7 6 5 4 3 2 1 0 TEST PWME — — OEB OEA OS CKS Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W Bit Clock select 0 Resolution (T) = system clock cycle time (tcyc) 1 Resolution (T) = system clock cycle time (tcyc) × 2 Output select 0 Direct PWM output 1 Inverted PWM output Output enable A 0 PWM channel A output (PWX0 output pin) disabled 1 PWM channel A output (PWX
PAGE 986
Appendix B Internal I/O Registers DACNTH—PWM (D/A) Counter H DACNTL—PWM (D/A) Counter L H'FFA6 H'FFA7 PWMX PWMX DACNTH DACNTL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit (counter) 7 6 5 4 3 2 1 0 8 9 10 11 12 13 — — — REGS Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — 1 R/W Register select Up-counter Rev. 4.
PAGE 987
Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 TCSR0 Bit H'FFA8 7 6 5 OVF WT/IT TME Initial value 0 0 0 0 Read/Write R/(W)* R/W R/W R/W 4 WDT0 3 2 1 0 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W RSTS RST/NMI Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 0 φ/2 1 φ/64 0 φ/128 1 φ/512 0 φ/2048 1 φ/8192 0 φ/32768 1 φ/131072 1 1 0 1 Clock Reset or NMI 0 NMI interrupt requested 1 Internal reset requested Reserved bit Timer enable 0 TCN
PAGE 988
Appendix B Internal I/O Registers TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 H'FFA8 (W), H'FFA9 (R) H'FFEA (W), H'FFEB (R) WDT0 WDT1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Up-counter P1PCR—Port 1 MOS Pull-Up Control Register Bit 7 6 5 4 H'FFAC 3 Port 1 2 1 0 P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Control of
PAGE 989
Appendix B Internal I/O Registers P1DDR—Port 1 Data Direction Register Bit 7 6 5 H'FFB0 4 Port 1 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Specification of input or output for port 1 pins P2DDR—Port 2 Data Direction Register Bit 7 6 5 H'FFB1 4 Port 2 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Spe
PAGE 990
Appendix B Internal I/O Registers P3DDR—Port 3 Data Direction Register Bit 7 6 5 H'FFB4 4 Port 3 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Specification of input or output for port 3 pins P4DDR—Port 4 Data Direction Register Bit 7 6 5 H'FFB5 4 Port 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Spe
PAGE 991
Appendix B Internal I/O Registers P5DDR—Port 5 Data Direction Register H'FFB8 Port 5 7 6 5 4 3 — — — — — Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — W W W Bit 2 1 0 P52DDR P51DDR P50DDR Specification of input or output for port 5 pins P6DDR—Port 6 Data Direction Register Bit 7 6 5 H'FFB9 4 Port 6 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Specification of inp
PAGE 992
Appendix B Internal I/O Registers P8DDR—Port 8 Data Direction Register Bit 7 — 6 5 H'FFBD 4 3 Port 8 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write — W W W W W W W Specification of input or output for port 8 pins P7PIN—Port 7 Input Data Register Bit 7 P77PIN 6 H'FFBE 5 4 3 Port 7 2 P76PIN P75PIN P74PIN P73PIN P72PIN 1 0 P71PIN P70PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Por
PAGE 993
Appendix B Internal I/O Registers P9DDR—Port 9 Data Direction Register Bit 7 6 H'FFC0 5 4 Port 9 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Mode 1 Initial value 0 1 0 0 0 0 0 0 Read/Write W W W W W W W W Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 Specification of input or output for port 9 pins P9DR—Port 9 Data Register Bit H'FFC1 Port 9 7 6 5 4 3 2 1 0 P97DR P96DR P95DR P94DR P93DR P92DR P91D
PAGE 994
Appendix B Internal I/O Registers STCR—Serial Timer Control Register H'FFC3 System 7 6 5 4 3 2 1 0 — IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Internal Clock Source Select 1 and 0*1 Reserved Flash memory control register enable 0 Flash memory control register not selected 1 Flash memory control register selected I2C master enable 0 CPU access to SCI0, SCI1, and SCI2 control registers is enable
PAGE 995
Appendix B Internal I/O Registers SYSCR—System Control Register Bit H'FFC4 System 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W RAM Enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled Host interface enable 0 Addresses H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF are used for access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection
PAGE 996
Appendix B Internal I/O Registers MDCR—Mode Control Register H'FFC5 System 7 6 5 4 3 2 1 0 EXPE — — — — — MDS1 MDS0 Initial value —* 0 0 0 0 0 —* —* Read/Write R/W* — — — — — R R Bit Mode pin state Expanded mode enable 0 Single-chip mode selected 1 Expanded mode selected Note: * Determined by the MD1 and MD0 pins. Rev. 4.
PAGE 997
Appendix B Internal I/O Registers BCR—Bus Control Register H'FFC6 7 6 ICIS1 ICIS0 Initial value 1 1 0 1 Read/Write R/W R/W R/W R/W Bit 5 4 3 Bus Controller 2 1 0 — IOS1 IOS0 0 1 1 1 R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 IOS select IOS1 IOS0 Addresses for which AS/IOS is low output when IOSE = 1 0 1 0 Low output when accessing addresses H'(FF)F000 to H'(FF)F03F 1 Low output when accessing addresses H'(FF)F000 to H'(FF)F0FF 0 Low output when accessing addresses H'(FF)
PAGE 998
Appendix B Internal I/O Registers WSCR—Wait State Control Register H'FFC7 Bus Controller 7 6 5 4 3 2 1 0 RAMS RAM0 ABW AST WMS1 WMS0 WC1 WC0 Initial value 0 0 1 1 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Wait count 1 and 0 0 1 Reserved Note: Always write 0 when writing to these bits in the A-mask version.
PAGE 999
Appendix B Internal I/O Registers TCR0—Timer Control Register 0 TCR1—Timer Control Register 1 TCRX—Timer Control Register X TCRY—Timer Control Register Y H'FFC8 H'FFC9 H'FFF0 H'FFF0 TMR0 TMR1 TMRX TMRY 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Clock select 2 to 0 Channel Bit 2 Bit 1 Bit 0 Description CKS2 CKS1 CKS0 Counter clear 1 and 0 0 1 0 1 0 0 Clear is disabled
PAGE 1000
Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 TCSR0 Bit H'FFCA TMR0 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 out
PAGE 1001
Appendix B Internal I/O Registers TCSR1—Timer Control/Status Register 1 TCSR1 Bit H'FFCB TMR1 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* — R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 output a
PAGE 1002
Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 TCORAY—Time Constant Register AY TCORBY—Time Constant Register BY TCORC—Time Constant Register C TCORAX—Time Constant Register AX TCORBX—Time Constant Register BX H'FFCC H'FFCD H'FFCE H'FFCF H'FFF2 H'FFF3 H'FFF5 H'FFF6 H'FFF7 TMR0 TMR1 TMR0 TMR1 TMRY TMRY TMRX TMRX TMRX TCORA0 TCORB0 TCORA1 TCORB1 Bit 15 14 13 12 11 10 9 8 7 6
PAGE 1003
Appendix B Internal I/O Registers TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNTX—Timer Counter X TCNTY—Timer Counter Y H'FFD0 H'FFD1 H'FFF4 H'FFF4 TMR0 TMR1 TMRX TMRY TCNT0 TCNT1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TCNTX, TCNTY Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W
PAGE 1004
Appendix B Internal I/O Registers PWOERA—PWM Output Enable Register A PWOERB—PWM Output Enable Register B H'FFD3 H'FFD2 PWM PWM 7 6 5 4 3 2 1 0 PWOERA OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Bit Bit PWOERB Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Switching between PWM output and port ou
PAGE 1005
Appendix B Internal I/O Registers PWSL—PWM Register Select 7 Bit H'FFD6 6 PWCKE PWCKS PWM 5 4 3 2 1 0 — — RS3 RS2 RS1 RS0 Initial value 0 0 1 0 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W Register Select 0 0 0 0 PWDR0 selected 1 PWDR1 selected 1 0 PWDR2 selected 1 PWDR3 selected 1 0 0 PWDR4 selected 1 PWDR5 selected 1 0 PWDR6 selected 1 PWDR7 selected 1 0 0 0 PWDR8 selected 1 PWDR9 selected 1 0 PWDR10 selected 1 PWDR11 selected 1 0 0 PWDR12 selected
PAGE 1006
Appendix B Internal I/O Registers PWDR0 to PWDR15—PWM Data Registers H'FFD7 PWM Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Specifies duty factor of basic output pulse and number of additional pulses ADDRAH—A/D Data Register AH ADDRAL—A/D Data Register AL ADDRBH—A/D Data Register BH ADDRBL—A/D Data Register BL ADDRCH—A/D Data Register CH ADDRCL—A/D Data Register CL ADDRDH—A/D Data Register DH ADDRDL—A/D Data Register DL H'FFE0
PAGE 1007
Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register H'FFE8 A/D Converter 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Bit Channel select Group selection Channel selection CH2 CH1 CH0 0 0 1 1 0 1 Description Single mode Scan mode 0 AN0 AN0 1 AN1 AN0, AN1 0 AN2 AN0, AN1, AN2 1 AN3 AN0, AN1, AN2, AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 or CIN0–CIN7 AN4
PAGE 1008
Appendix B Internal I/O Registers ADCR—A/D Control Register H'FFE9 A/D Converter 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — — — — — Initial value 0 0 1 1 1 1 1 1 Read/Write R/W R/W — — — — — — Bit Timer trigger select 0 1 0 Start of A/D conversion by external trigger is disabled 1 Start of A/D conversion by external trigger is disabled 0 Start of A/D conversion by external trigger (8-bit timer) is enabled 1 Start of A/D conversion by external trigger pin is enabled Rev.
PAGE 1009
Appendix B Internal I/O Registers TCSR1—Timer Control/Status Register 1 TCSR1 Bit H'FFEA WDT1 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)*1 R/W R/W R/W R/W R/W R/W R/W Clock select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock 0 φ/2 1 φ/64 0 φ/128 1 φ/512 0 φ/2048 1 φ/8192 0 φ/32768 1 φ/131072 0 φSUB/2 1 φSUB/4 0 φSUB/8 1 φSUB/16 0 φSUB/32 1 φSUB/64 0 φS
PAGE 1010
Appendix B Internal I/O Registers HICR—Host Interface Control Register H'FFF0 HIF 7 6 5 4 3 2 — — — — — IBFIE2 Initial value 1 1 1 1 1 0 0 0 Slave R/W — — — — — R/W R/W R/W Host R/W — — — — — — — — Bit 1 0 IBFIE1 FGA20E Fast gate A20 enable 0 Fast gate A20 function disabled 1 Fast gate A20 function enabled Input data register interrupt enable 1 0 Input data register (IDR1) receive complete interrupt is disabled 1 Input data register (IDR1) receive comple
PAGE 1011
Appendix B Internal I/O Registers TCSRX—Timer Control/Status Register X TCSRX Bit H'FFF1 TMRX 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 o
PAGE 1012
Appendix B Internal I/O Registers TCSRY—Timer Control/Status Register Y TCSRY Bit H'FFF1 TMRY 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 out
PAGE 1013
Appendix B Internal I/O Registers KMIMR—Keyboard Matrix Interrupt Mask Register H'FFF1 Interrupt Controller KMIMR Bit 7 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Keyboard matrix interrupt mask 0 Key-sense input interrupt requests enabled 1 Key-sense input interrupt requests disabled* Note: * However, the initial value of KMIMR6 is 0 because the KMIMR6 bit controls both IRQ6
PAGE 1014
Appendix B Internal I/O Registers IDR1—Input Data Register 1 IDR2—Input Data Register 2 H'FFF4 H'FFFC HIF HIF 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value — — — — — — — — Slave R/W R R R R R R R R Host R/W W W W W W W W W Bit Stores host data bus contents at rise of IOW when CS is low ODR1—Output Data Register 1 ODR2—Output Data Register 2 H'FFF5 H'FFFD HIF HIF 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
PAGE 1015
Appendix B Internal I/O Registers STR1—Status Register 1 STR2—Status Register 2 H'FFF6 H'FFFE HIF HIF 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF Initial value 0 0 0 0 0 0 0 0 Slave R/W R/W R/W R/W R/W R R/W R R/(W) Host R/W R R R R R R R R Bit User-defined bits Output data register full 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit 1 [Setting condition] When the slave processor writes to ODR Input data
PAGE 1016
Appendix B Internal I/O Registers DACR—D/A Control Register H'FFFA D/A Converter 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W — — — — — Bit D/A enabled DAOE1 DAOE0 0 1 DAE Conversion result 0 * Channel 0 and 1 D/A conversion disabled 1 0 Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 Channel 0 and 1 D/A conversion enabled 0 Channel 0 D/A conversion disabled Channel 1 D/A conversion ena
PAGE 1017
Appendix B Internal I/O Registers TCONRI—Timer Connection Register I Bit 7 6 H'FFFC 5 SIMOD1 SIMOD0 SCONE Timer Connection 4 3 2 1 0 ICST HFINV VFINV HIINV VIINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Input synchronization signal inversion 0 The VSYNCI pin state is used directly as the VSYNCI input 1 The VSYNCI pin state is inverted before use as the VSYNCI input Input synchronization signal inversion 0 The HSYNCI and CSYNCI pin stat
PAGE 1018
Appendix B Internal I/O Registers TCONRO—Timer Connection Register O H'FFFD Timer Connection 7 6 5 4 3 2 HOE VOE CLOE CBOE HOINV VOINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 1 CLOINV CBOINV Output synchronization signal inversion 0 The CBLANK signal is used directly as the CBLANK output 1 The CBLANK signal is inverted before use as the CBLANK output Output synchronization signal inversion 0 The CLO signal (CL1, CL2, CL3, or C
PAGE 1019
Appendix B Internal I/O Registers TCONRS—Timer Connection Register S 7 Bit 6 TMRX/Y 5 H'FFFE 4 3 Timer Connection 2 1 0 ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clamp waveform mode select 1 and 0 ISGENE CLMOD1 CLMOD0 0 0 1 Description 0 The CL1 signal is selected 1 The CL2 signal is selected 0 The CL3 signal is selected 1 1 0 The CL4 signal is selected 0 1 1 0 1 Vertical synchroniza
PAGE 1020
Appendix B Internal I/O Registers SEDGR—Edge Sense Register Bit Initial value Read/Write H'FFFF 7 6 5 4 VEDG HEDG CEDG 0 1 R/(W)* 0 1 R/(W)* 0 1 R/(W)* Timer Connection 2 3 1 HFEDG VFEDG PREQF 0 1 R/(W)* 0 1 R/(W)* 0 1 R/(W)* 0 IHI —*2 IVI —*2 R R IVI signal level 0 The IVI signal is low 1 The IVI signal is high IHI signal level 0 The IHI signal is low 1 The IHI signal is high Pre-equalization flag 0 [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 1
PAGE 1021
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Mode 2, 3 EXPE Mode 1 RP1P Hardware standby Mode 1 WP1P Reset R D Q P1nDDR C WP1D Reset P1n Internal address bus R Q D P1nPCR C Internal data bus Reset 8-bit PWM PWM output enable PWM output R Q D P1nDR C WP1 RP1 Legend: WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 Note: n = 0 to 7 Figure C.1 Port 1 Block Diagram Rev. 4.
PAGE 1022
Appendix C I/O Port Block Diagrams C.2 Port 2 Block Diagrams Mode 2, 3 EXPE Mode 1 RP2P Hardware standby Mode 1 WP2P Reset R D Q P2nDDR C WP2D Reset P2n R Q D P2nDR C WP2 RP2 Legend: WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 Note: n = 0 to 3 Figure C.2 Port 2 Block Diagram (Pins P20 to P23) Rev. 4.
PAGE 1023
Appendix C I/O Port Block Diagrams Mode 2, 3 EXPE IOSE Mode 1 RP2P Hardware standby Mode 1 WP2P Reset R D Q P2nDDR * C WP2D Reset P2n Internal address bus R Q D P2nPCR C Internal data bus Reset 8-bit PWM PWM output enable PWM output R Q D P2nDR C WP2 RP2 Legend: WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 Note: n = 4 to 6 Figure C.3 Port 2 Block Diagram (Pins P24 to P26) Rev. 4.
PAGE 1024
Appendix C I/O Port Block Diagrams Mode 2, 3 EXPE IOSE Mode 1 RP2P Hardware standby WP2P Reset Mode 1 R D Q P27DDR C WP2D Reset P27 Internal address bus R Q D P27PCR C Internal data bus Reset 8-bit PWM PWM output enable PWM output R Q D P27DR C Mode 2, 3 WP2 Timer connection CBLANK CBLANK output enable RP2 Legend: WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 Figure C.4 Port 2 Block Diagram (Pin P27) Rev. 4.
PAGE 1025
Appendix C I/O Port Block Diagrams Port 3 Block Diagram Mode 2, 3 EXPE HI12E Mode 1 R Q D P3nPCR C RP3P Hardware standby WP3P Reset CS IOR R D Q P3nDDR C External address write Host interface data bus Reset Internal data bus C.3 WP3D Reset P3n CS IOW R Q D P3nDR C WP3 RP3 External address read Legend: WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to port 3 RP3P: Read P3PCR RP3: Read port 3 Note: n = 0 to 7 Figure C.5 Port 3 Block Diagram Rev. 4.
PAGE 1026
Appendix C I/O Port Block Diagrams Port 4 Block Diagrams Hardware standby Reset R D Q P40DDR C WP4D Internal data bus C.4 SCI2 TxD2/IrTxD Transmit enable Reset P40 R Q D P40DR C WP4 RP4 8-bit timer 0 Counter clock input Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.6 Port 4 Block Diagram (Pin P40) Rev. 4.
PAGE 1027
Hardware standby Reset R D Q P41DDR C WP4D Internal data bus Appendix C I/O Port Block Diagrams 8-bit timer 0 8-bit timer output Output enable Reset P41 R Q D P41DR C WP4 RP4 SCI2 Receive enable RxD2/IrRxD Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.7 Port 4 Block Diagram (Pin P41) Rev. 4.
PAGE 1028
Hardware standby Reset R D Q P42DDR C Internal data bus Appendix C I/O Port Block Diagrams WP4D SCI2 Input enable Clock output Output enable Reset Clock output *1 R Q D P42DR C P42 *2 WP4 IIC1 SDA1 output Transmit enable RP4 SDA1 input Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Notes: 1. Output enable signal 2. Open drain control signal Figure C.8 Port 4 Block Diagram (Pin P42) Rev. 4.
PAGE 1029
Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Reset R D Q P43DDR C WP4D Reset R Host interface RESOBF2 (resets HIRQ11) Q D P43DR C P43 WP4 RP4 8-bit timer 1 Counter clock input Timer connection Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 HSYNCI input Figure C.9 Port 4 Block Diagram (Pin P43) Rev. 4.
PAGE 1030
Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Reset R D Q P44DDR C WP4D Timer connection HSYNCO output Output enable Reset R Q D P44DR C P44 WP4 RP4 Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.10 Port 4 Block Diagram (Pin P44) Rev. 4.
PAGE 1031
Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Reset R D Q P45DDR C WP4D Reset R Host interface RESOBF1 (resets HIRQ12) Q D P45DR C P45 WP4 RP4 8-bit timer 1 Timer reset input Timer connection Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 CSYNCI input Figure C.11 Port 4 Block Diagram (Pin P45) Rev. 4.
PAGE 1032
Hardware standby Reset R D Q P4nDDR C WP4D Internal data bus Appendix C I/O Port Block Diagrams 14-bit PWM PWX0, PWX1 output Output enable Reset P4n R Q D P4nDR C WP4 RP4 Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Note: n = 6 or 7 Figure C.12 Port 4 Block Diagram (Pins P46, P47) Rev. 4.
PAGE 1033
Appendix C I/O Port Block Diagrams Port 5 Block Diagrams Hardware standby Reset R D Q P50DDR C WP5D Internal data bus C.5 SCI0 Serial transmit data Output enable Reset P50 R Q D P50DR C WP5 RP5 Legend: WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.13 Port 5 Block Diagram (Pin P50) Rev. 4.
PAGE 1034
Hardware standby Reset R D Q P51DDR C Internal data bus Appendix C I/O Port Block Diagrams WP5D SCI0 Input enable Reset R Q D P51DR C P51 WP5 RP5 Legend: WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.14 Port 5 Block Diagram (Pin P51) Rev. 4.
PAGE 1035
Hardware standby Reset R D Q P52DDR C WP5D *1 Reset R Q D P52DR C P52 *2 WP5 Internal data bus Appendix C I/O Port Block Diagrams SCI0 Input enable Clock output Output enable Clock input IIC0 SCL0 output Transmit enable RP5 SCL0 input Legend: WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Notes: 1. Output enable signal 2. Open drain control signal Figure C.15 Port 5 Block Diagram (Pin P52) Rev. 4.
PAGE 1036
Appendix C I/O Port Block Diagrams C.
PAGE 1037
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset Internal data bus Reset R D Q P61DDR C WP6D 16-bit FRT FTOA output Output enable Reset R Q D P61DR C P61 WP6 Timer connection VSYNCO output Output enable RP6 Key-sense interrupt input KMIMR1 A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.17 Port 6 Block Diagram (Pin P61) Rev. 4.
PAGE 1038
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P64DDR C WP6D Internal data bus Reset Timer connection CLAMPO output Output enable Reset P64 R Q D P64DR C WP6 RP6 16-bit FRT FTIC input Key-sense interrupt input KMIMR4 A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.18 Port 6 Block Diagram (Pin P64) Rev. 4.
PAGE 1039
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P WP6P Hardware standby Reset R D Q P66DDR C WP6D Internal data bus Reset 16-bit FRT FTOB output Output enable Reset P66 R Q D P66DR C WP6 RP6 KMIMR6 Other key-sense interrupt inputs IRQ6 input IRQ6 enable A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.19 Port 6 Block Diagram (Pin P66) Rev. 4.
PAGE 1040
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P67DDR C WP6D Internal data bus Reset 8-bit timer X TMOX output Output enable Reset P67 R Q D P67DR C WP6 RP6 IRQ7 input IRQ7 enable A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.20 Port 6 Block Diagram (Pin P67) Rev. 4.
PAGE 1041
Appendix C I/O Port Block Diagrams Internal data bus Port 7 Block Diagrams RP7 P7n A/D converter Analog input Legend: RP7: Read port 7 Note: n = 0 to 5 Figure C.21 Port 7 Block Diagram (Pins P70 to P75) Internal data bus C.7 RP7 P7n A/D converter Analog input D/A converter Output enable Analog output Legend: RP7: Read port 7 Note: n = 6 or 7 Figure C.22 Port 7 Block Diagram (Pins P76, P77) Rev. 4.
PAGE 1042
Appendix C I/O Port Block Diagrams Port 8 Block Diagrams HI12E EXPE Mode 2, 3 Hardware standby Reset R D Q P80DDR C Internal data bus C.8 WP8D Reset R Q D P80DR C P80 WP8 RP8 HIF HA0 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.23 Port 8 Block Diagram (Pin P80) Rev. 4.
PAGE 1043
Hardware standby Reset Mode 2, 3 EXPE CS2E HI12E R D Q P81DDR C WP8D Internal data bus Appendix C I/O Port Block Diagrams HIF GA20 output Output enable Reset P81 R Q D P81DR C WP8 RP8 HIF CS2 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.24 Port 8 Block Diagram (Pin P81) Rev. 4.
PAGE 1044
Hardware standby Reset R D Q P8nDDR C Internal data bus Appendix C I/O Port Block Diagrams WP8D Reset R Q D P8nDR C P8n WP8 RP8 HIF HIFSD input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Mode 2, 3 EXPE HI12E Note: n = 2, 3 Figure C.25 Port 8 Block Diagram (Pins P82, P83) Rev. 4.
PAGE 1045
Hardware standby Reset R D Q P84DDR C WP8D Internal data bus Appendix C I/O Port Block Diagrams SCI1 TxD1 Transmit enable Reset P84 R Q D P84DR C WP8 RP8 IRQ3 input IRQ3 enable Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.26 Port 8 Block Diagram (Pin P84) Rev. 4.
PAGE 1046
Hardware standby Reset R D Q P85DDR C Internal data bus Appendix C I/O Port Block Diagrams SCI1 WP8D Input enable Reset R Q D P85DR C P85 WP8 RP8 Serial receive data IRQ4 input IRQ4 enable Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.27 Port 8 Block Diagram (Pin P85) Rev. 4.
PAGE 1047
Hardware standby Reset Internal data bus Appendix C I/O Port Block Diagrams R D Q P86DDR C WP8D *1 Reset SCI1 Input enable Clock output Output enable Clock input R Q D P86DR C P86 *2 WP8 IIC1 SCL1 output Transmit enable RP8 SCL1 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 IRQ5 input IRQ5 enable Notes: 1. Output enable signal 2. Open drain control signal Figure C.28 Port 8 Block Diagram (Pin P86) Rev. 4.
PAGE 1048
Appendix C I/O Port Block Diagrams Port 9 Block Diagrams Hardware standby EXPE Mode 2, 3 GA20 HI12E CS2E Reset R D Q P90DDR C Internal data bus C.9 WP9D Reset R Q D P90DR C P90 WP9 RP9 HIF ECS2 input A/D converter External trigger input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.29 Port 9 Block Diagram (Pin P90) Rev. 4.
PAGE 1049
Hardware standby Reset R D Q P9nDDR C Internal data bus Appendix C I/O Port Block Diagrams WP9D Reset R Q D P9nDR C P9n WP9 RP9 IRQ1 input IRQ0 input IRQ1 enable IRQ0 enable Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 1 or 2 Figure C.30 Port 9 Block Diagram (Pins P91, P92) Rev. 4.
PAGE 1050
Hardware standby Mode 2, 3 EXPE HI12E EXPE Reset Internal data bus Appendix C I/O Port Block Diagrams R D Q P9nDDR C WP9D Reset P9n Bus controller RD output WR output AS/IOS output R Q D P9nDR C WP9 RP9 HIF Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Mode 2, 3 EXPE HI12E Note: n = 3 to 5 Figure C.31 Port 9 Block Diagram (Pins P93 to P95) Rev. 4.
PAGE 1051
Reset Mode 1 Internal data bus Appendix C I/O Port Block Diagrams Hardware standby S R D Q P96DDR C Subclock input enable WP9D φ output P96 RP9 Subclock input Legend: WP9D: Write to P9DDR RP9: Read port 9 Figure C.32 Port 9 Block Diagram (Pin P96) Rev. 4.
PAGE 1052
Hardware standby Reset R D Q P97DDR C WP9D Internal data bus Appendix C I/O Port Block Diagrams Bus controller Input enable EXPE *1 Reset R Q D P97DR C P97 *2 WP9 WAIT input IIC0 SDA0 output Transmit enable RP9 SDA0 input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Notes: 1. Output enable signal 2. Open drain control signal Figure C.33 Port 9 Block Diagram (Pin P97) Rev. 4.
PAGE 1053
Appendix D Pin States Appendix D Pin States D.1 Port States in Each Processing State Table D.
PAGE 1054
Appendix D Pin States Port Name Pin Name Port 96 φ EXCL Hardware Software MCU Operating Standby Standby Mode Reset Mode Mode 1 Clock T output 2, 3 (EXPE = 1) T Watch Mode [DDR = 1] H EXCL input [DDR = 0] T 1 H 2, 3 (EXPE = 1) T T 2, 3 (EXPE = 0) Port 92 to 90 1 [DDR = 1] clock output Subsleep Mode Subactive Mode Program Execution State EXCL input EXCL input Clock output/ EXCL input/ input port [DDR = 0] T 2, 3 (EXPE = 0) Port 95 to 93 AS, WR, RD Sleep Mode T T H H H H AS, WR,
PAGE 1055
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode E.1 Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown in figure E.1. RES must remain low until STBY signal goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 ≥ 10tcyc t2 ≥ 0 ns RES Figure E.
PAGE 1056
Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.
PAGE 1057
Appendix F Product Code Lineup Product Type H8S/2134 Group H8S/2134 Mask ROM version F-ZTAT version Mark Code Standard product (5 V version, 4 V version, 3 V version) HD6432134S HD6432134S(V)(***)FA 80-pin QFP (FP-80A) HD6432134S(V)(***)TF 80-pin TQFP (TFP-80C) Standard product (5 V/4 V version) HD64F2134 HD64F2134FA20 80-pin QFP (FP-80A) HD64F2134TF20 80-pin TQFP (TFP-80C) HD64F2134VFA10 80-pin QFP (FP-80A) HD64F2134VTF10 80-pin TQFP (TFP-80C) HD6432133S(V)(***)FA 80-pin QFP (FP-80A)
PAGE 1058
Appendix G Package Dimensions Appendix G Package Dimensions Figures G.1 and G.2 show the package dimensions of the H8S/2138 Group and H8S/2134 Group. JEITA Package Code P-QFP80-14x14-0.65 RENESAS Code PRQP0080JB-A Previous Code FP-80A/FP-80AV MASS[Typ.] 1.2g HD *1 D 60 41 61 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
PAGE 1059
Appendix G Package Dimensions JEITA Package Code P-TQFP80-12x12-0.50 RENESAS Code PTQP0080KC-A Previous Code TFP-80C/TFP-80CV MASS[Typ.] 0.4g HD *1 D 60 41 61 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 40 bp c c1 HE *2 E b1 Reference Dimension in Millimeters Symbol Terminal cross section ZE F c A2 Index mark A 20 1 ZD θ A1 L L1 e *3 y bp Detail F x M Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.
PAGE 1060
Appendix G Package Dimensions Rev. 4.
PAGE 1061
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2138 Group, H8S/2134 Group, H8S/2138F-ZTAT™, H8S/2134F-ZTAT™, H8S/2132F-ZTAT™ Publication Date: 1st Edition, December 1997 Rev.4.00, June 06, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
PAGE 1062
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
PAGE 1063
H8S/2138 Group, H8S/2134 Group, H8S/2138F-ZTAT™, H8S/2134F-ZTAT™, H8S/2132F-ZTAT™ Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0301-0400