Datasheet

Appendix
Rev. 3.00 Sep. 28, 2009 Page 899 of 910
REJ09B0350-0300
Appendix
A. I/O Port States in Each Pin State
Table A.1 I/O Port States in Each Pin State
Port Name
Pin Name Reset
Software
Standby Mode Watch Mode Sleep Mode
Program
Execution State
Port 1 T keep keep keep I/O port
Port 2 T keep keep keep I/O port
Port 3 T keep keep keep I/O port
Port 4 T keep keep keep I/O port
Ports 52 to 50 T keep keep keep I/O port
Port 6 T keep keep keep I/O port
Ports 7 and E4 to
E1
T T T T Input port
Port 8 T keep keep keep I/O port
Port 97 T keep keep keep I/O port
Port 96
φ,
EXCL
T [DDR = 1]H
[DDR = 0]T
EXCL input/
keep
[DDR = 1]
Clock output
[DDR = 0]T
Clock output/
EXCL input/
Input port
Ports 95 to 90 T keep keep keep I/O port
Ports A to D,
F, G, and H5 to H0
T keep keep keep I/O port
Port E0 T T ExEXCL input/T T ExEXCL input/
input port
Port I T keep keep keep I/O port
Port J T keep keep keep I/O port
[Legend]
H: High level
L: Low level
T: High impedance
keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up
MOS remains on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR.
DDR: Data direction register