Datasheet

Section 26 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 894 of 910
REJ09B0350-0300
Test voltage: 0.4Vcc
50 pF
Figure 26.25 Test Conditions for Tester
Table 26.11 JTAG Timing
Conditions: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V, φ = 8 MHz to 20 MHz
Item Symbol Min. Max. Unit
Test
Conditions
ETCK clock cycle time t
TCKcyc
50* 125*
ETCK clock high pulse width t
TCKH
20 ⎯
ETCK clock low pulse width t
TCKL
20 ⎯
ETCK clock rise time t
TCKr
⎯ 5
ETCK clock fall time t
TCKf
⎯ 5
ns Figure
26.26
ETRST pulse width t
TRSTW
20 ⎯
Reset hold transition pulse width t
RSTHW
3 ⎯
t
cyc
Figure
26.27
ETMS setup time t
TMSS
20 ⎯
ETMS hold time t
TMSH
20 ⎯
ETDI setup time t
TDIS
20 ⎯
ETDI hold time t
TDIH
20 ⎯
ns Figure
26.28
ETDO data delay time t
TDOD
⎯ 20
Note: * When t
cyc
≤ t
TCKcyc
ETCK
t
TCKH
t
TCKf
t
TCKcyc
t
TCKL
t
TCKr
Figure 26.26 JTAG ETCK Timing