Datasheet

Section 26 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 893 of 910
REJ09B0350-0300
Table 26.10 LPC Timing
Conditions: V
CC
= 3.0 V to 3.6V, V
SS
= 0 V, φ = 8 MHz to maximum operating frequency,
Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Input clock cycle t
Lcyc
30 ⎯ ⎯
Input clock pulse width (H) t
LCKH
11 ⎯ ⎯
Input clock pulse width (L) t
LCKL
11 ⎯ ⎯
Transmit signal delay time t
TXD
2 ⎯ 11
Transmit signal floating delay
time
t
OFF
⎯ ⎯ 28
Receive signal setup time t
RXS
7 ⎯ ⎯
ns Figure
26.24
Receive signal hold time t
RXH
0 ⎯ ⎯
LCLK
LAD3 to LAD0,
SERIRQ, CLKRUN
(transmit signal)
LAD3 to LAD0,
SERIRQ, CLKRUN,
LFRAME
(receive signal)
t
TXD
t
RXH
t
RXS
t
OFF
LAD3 to LAD0,
SERIRQ, CLKRUN
(transmit signal)
t
Lcyc
t
LCKH
LCLK
t
LCKL
Figure 26.24 LPC Interface Timing