Datasheet

Section 26 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 890 of 910
REJ09B0350-0300
t
Scyc
t
SCKr
t
SCKW
SCK1
t
SCKf
Figure 26.20 SCK Clock Input Timing
SCK1
TxD1
(transmit data)
RxD1
(receive data)
t
TXD
t
RXH
t
RXS
Figure 26.21 SCI Input/Output Timing (Clock Synchronous Mode)
Table 26.8 PS2 Timing
Conditions: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V, φ = 8 MHz to maximum operating frequency
Standard Value
Item Symbol Min. Typ. Max. Unit
Test
Conditions Remarks
KCLK, KD output fall time t
KBF
⎯ ⎯ 250 ns
KCLK, KD input data hold time t
KBIH
150 ⎯ ⎯
KCLK, KD input data setup time t
KBIS
150 ⎯ ⎯
KCLK, KD output delay time t
KBOD
⎯ ⎯ 450
Figure
26.22
KCLK, KD capacitive load C
b
⎯ ⎯ 400 pF
Note: * When KCLK and KD are output, an external pull-up register must be connected, as
shown in figure 26.22.