Datasheet

Section 26 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 887 of 910
REJ09B0350-0300
Item Symbol Min. Max. Unit
Test
Conditions
Input clock rise time t
SCKr
⎯ 1.5
Input clock fall time t
SCKf
⎯ 1.5
t
cyc
Figure 26.20
Transmit data delay time (synchronous) t
TXD
⎯ 50
SCI
Receive data setup time (synchronous) t
RXS
50 ⎯
ns Figure 26.21
Receive data hold time (synchronous) t
RXH
50 ⎯
Notes: 1. Applied only for the peripheral modules that are available during subclock operation.
2. Other than P52, P97, P86, P42, port A, port G, and port I.
φ
Ports 1 to 9
and A to J (read)
t
PRS
T
1
T
2
t
PWD
t
PRH
Ports 1 to 6, 8, 9,
A to D and F to J
(write)
Figure 26.9 I/O Port Input/Output Timing
Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, and TIOCD0
φ
Output compare
outputs*
Input capture
inputs*
t
TOCD
t
TICS
Figure 26.10 TPU Input/Output Timing