Datasheet

Section 26 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 886 of 910
REJ09B0350-0300
26.3.3 Timing of On-Chip Peripheral Modules
Tables 26.7 to 26.9 show the on-chip peripheral module timing. The on-chip peripheral modules
that can be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI,
IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer
(WDT_1) only.
Table 26.7 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V, φ = 32.768 kHz*
1
, φ = 8 MHz to maximum
operating frequency
Item Symbol Min. Max. Unit
Test
Conditions
Output data delay time*
2
t
PWD
⎯ 50
Input data setup time t
PRS
30 ⎯
I/O ports
Input data hold time t
PRH
30 ⎯
ns Figure 26.9
Timer output delay time t
TOCD
⎯ 50
Timer input setup time t
TICS
30 ⎯
Figure 26.10
Timer clock input setup time t
TCKS
30 ⎯
ns
Single edge t
TCKWH
1.5 ⎯
TPU
Timer clock
pulse width
Both edges t
TCKWL
2.5 ⎯
t
cyc
Figure 26.11
Timer output delay time t
TMOD
⎯ 50 Figure 26.12
Timer reset input setup time t
TMRS
30 ⎯ Figure 26.14
Timer clock input setup time t
TMCS
30 ⎯
ns
Single edge t
TMCWH
1.5 ⎯
TMR
Timer clock
pulse width
Both edges t
TMCWL
2.5 ⎯
t
cyc
Figure 26.13
TCM input setup time t
TCMS
30 ⎯ Figure 26.15
TCM clock input setup time t
TCMCKS
30 ⎯
ns
TCM
TCM clock pulse width t
TCMCKW
1.5 ⎯ t
cyc
Figure 26.16
TDP input setup time t
TDPS
30 ⎯ Figure 26.17
TDP clock input setup time t
TDPCKS
30 ⎯
ns
TDP
TDP clock pulse width t
TDPCKW
1.5 ⎯ t
cyc
Figure 26.18
PWMU, PWMX Pulse output delay time t
PWOD
⎯ 50 ns Figure 26.19
Asynchronous t
Scyc
4 ⎯ SCI Input clock cycle
Synchronous 6 ⎯
t
cyc
Figure 26.20
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc