Datasheet

Section 26 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 882 of 910
REJ09B0350-0300
26.3.1 Clock Timing
Table 26.5 shows the clock timing. The clock timing specified here covers clock output (φ) and
clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization
times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23,
Clock Pulse Generator.
Table 26.5 Clock Timing
Condition A: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V, φ = 8 MHz to 10 MHz
Condition B: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V, φ = 10 MHz to 20 MHz
Condition A Condition B
Item Symbol Min. Max. Min. Max. Unit Reference
Clock cycle time t
cyc
100 125 50 100
Clock high pulse width t
CH
30 ⎯ 20 ⎯
Clock low pulse width t
CL
30 ⎯ 20 ⎯
Clock rise time t
Cr
⎯ 20 ⎯ 5
Clock fall time t
Cf
⎯ 20 ⎯ 5
ns Figure 26.4
Reset oscillation stabilization (crystal) t
OSC1
20 ⎯ 20 ⎯ Figure 26.5
Software standby oscillation
stabilization time (crystal)
t
OSC2
8 ⎯ 8 ⎯
ms
Figure 26.6
External clock output stabilization delay
time
t
DEXT
500 ⎯ 500 ⎯ µs Figure 26.5
t
Cr
t
CL
t
Cf
t
CH
t
cyc
φ
Figure 26.4 System Clock Timing