Datasheet

Section 2 CPU
Rev. 3.00 Sep. 28, 2009 Page 39 of 910
REJ09B0350-0300
SP (ER7)
Free area
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0).
2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions, except for the STC instruction, are executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit Bit Name
Initial
Value
R/W Description
7 T 0 R/W Trace Bit
This bit has no effect on the operation of the MCU.
6 to 3 ⎯ All 1 ⎯ Reserved
These bits are always read as 1.
2
1
0
I2
I1
I0
1
1
1
R/W
R/W
R/W
Interrupt Request Mask Bits 2 to 0
These bits have no effect on the operation of the MCU.