Datasheet

Section 24 Power-Down Modes
Rev. 3.00 Sep. 28, 2009 Page 770 of 910
REJ09B0350-0300
24.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit Bit Name
Initial
Value
R/W Description
7 DTON 0 R/W Direct Transfer On Flag
The initial value should not be changed.
6 LSON 0 R/W Low-Speed On Flag
The initial value should not be changed.
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB)
input from the EXCL or ExEXCL pin is sampled using
the clock (φ) generated by the system clock pulse
generator. Clear this bit to 0 when φ is 5 MHz or more.
The initial value should not be changed.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock (not allowed)
4 EXCLE 0 R/W Subclock Input Enable
Enables or disables subclock input from the EXCL or
ExEXCL pin.
0: Disables subclock input from the EXCL or ExEXCL
pin
1: Enables subclock input from the EXCL or ExEXCL
pin
3 to 0 ⎯ All 0 R/W Reserved
The initial value should not be changed.