Datasheet

Section 24 Power-Down Modes
Rev. 3.00 Sep. 28, 2009 Page 768 of 910
REJ09B0350-0300
24.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name
Initial
Value
R/W Description
7 SSBY 0 R/W Software Standby
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-
speed mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode or watch mode
Note that the SSBY bit is not changed even if a mode
transition is made by an interrupt.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
On canceling software standby mode or watch mode,
these bits select the wait time for clock stabilization
from clock oscillation start. Select a wait time of 8 ms
(oscillation stabilization time) or more, depending on
the operating frequency. Table 24.2 shows the
relationship between the STS2 to STS0 values and
wait time.
With an external clock, an arbitrary wait time can be
selected. For normal cases, the minimum value is
recommended.
3 ⎯ 0 R/W Reserved
The initial value should not be changed.