Datasheet

Section 23 Clock Pulse Generator
Rev. 3.00 Sep. 28, 2009 Page 762 of 910
REJ09B0350-0300
Table 23.3 External Clock Input Conditions
VCC = 3.0 to 3.6 V
Item Symbol Min. Max. Unit Test Conditions
External clock input pulse
width low level
t
EXL
20 ⎯ ns
External clock input pulse
width high level
t
EXH
20 ⎯ ns
External clock rising time t
EXr
⎯ 5 ns
External clock falling time t
EXf
⎯ 5 ns
Figure 23.5
Clock pulse width low level t
CL
0.4 0.6 t
cyc
Figure 26.4
Clock pulse width high level t
CH
0.4 0.6 t
cyc
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 23.5 External Clock Input Timing
The oscillator and duty correction circuit can adjust the waveform of the external clock input that
is input from the EXTAL pin.
When a specified clock signal is input to the EXTAL pin, internal clock signal output is
determined after the external clock output stabilization delay time (t
DEXT
) has passed. As the clock
signal output is not determined during the t
DEXT
cycle, a reset signal should be set to low to
maintain the reset state. Table 23.4 shows the external clock output stabilization delay time. Figure
23.6 shows the timing of the external clock output stabilization delay time.