Datasheet

Section 22 Flash Memory
Rev. 3.00 Sep. 28, 2009 Page 683 of 910
REJ09B0350-0300
22.7 Register Descriptions
The flash memory has the following registers and parameters.
Table 22.3 Register Configuration
Register Name Abbreviation R/W
Initial
Value
Address
Data Bus
Width
Flash code control status register FCCS R/W* H'80 H'FEA8 8
Flash program code select register FPCS R/W H'00 H'FEA9 8
Flash erase code select register FECS R/W H'00 H'FEAA 8
Flash key code register FKEY R/W H'00 H'FEAC 8
Flash MAT select register FMATS R/W H'00 H'FEAD 8
Flash transfer destination address
register
FTDAR R/W H'00 H'FEAE 8
Note: * Bits other than the SCO bit are read-only bits. The SCO bit is a write-only bit and is
always read as 0.
Table 22.4 Parameter Configuration
Register Name Abbreviation R/W
Initial
Value
Address
Data Bus
Width
Download path fail result parameter DPFR R/W* Undefined On-chip
RAM*
8, 16, 32
Flash path/fail parameter FPFR R/W Undefined R0L of
CPU
8, 16, 32
Flash program/erase frequency
parameter
FPEFEQ R/W Undefined ER0 of
CPU
8, 16, 32
Flash multipurpose address area
parameter
FMPAR R/W Undefined ER1 of
CPU
8, 16, 32
Flash multipurpose data destination
parameter
FMPDR R/W Undefined ER0 of
CPU
8, 16, 32
Flash erase block select parameter FEBS R/W Undefined ER0 of
CPU
8, 16, 32
Note: * One byte of the start address on the on-chip RAM specified by FTDAR