Datasheet

Section 20 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 665 of 910
REJ09B0350-0300
20.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 20.2 shows the A/D conversion timing. Table 20.4 indicates
the A/D conversion time.
As indicated in figure 20.2, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of write to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 20.4.
In scan mode, the values shown in table 20.4 become those for the first conversion time. The
second and subsequent conversion times are listed in table 20.5. In either case, bits CKS1 and
CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the
A/D conversion characteristics.
(1)
(2)
t
D
t
SPL
t
CONV
Pφ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 20.2 A/D Conversion Timing