Datasheet

Section 20 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 663 of 910
REJ09B0350-0300
Bit Bit Name Initial Value R/W Description
0 ⎯ 0 R Reserved
This bit is always read as 0 and cannot be modified.
[Legend]
X: Don't care
Note: * Set the clock so that ADCLK ≤ 10 MHz.
20.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. First, select the clock used in A/D conversion.
When changing the operating mode or analog input channel, to prevent incorrect operation, first
clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set at the same
time the operating mode or analog input channel is changed.
20.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by
software, the TMR, or the TPU.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
1 at this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit
is automatically cleared to 0 and the A/D converter enters wait state. When the ADST bit is
cleared to 0 during A/D conversion, the conversion stops and the A/D converter enters wait
state.