Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 649 of 910
REJ09B0350-0300
their respective functional differences. In order to clear a host interrupt request, it is necessary to
clear the host interrupt enable bit. (n = 2 to 4.)
When the SCIF channels are used, clearing the DDCD bit in FMSR of the SCIF clears a host
interrupt request.
Table 19.10 summarizes the methods of setting and clearing these bits when the LPC channels are
used, and table 19.11 summarizes the methods of setting and clearing these bits when the SCIF
channels are used. Figure 19.8 shows the processing flowchart.