Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 648 of 910
REJ09B0350-0300
19.5 Interrupt Sources
19.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI
The host has six interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, OBEI, and
ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and
IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such
as an LPC reset, LPC shutdown, or transfer cycle abort. The LMCI and LMCUI interrupts are
command receive complete interrupts. OBEI is an output buffer empty interrupt. An interrupt
request is enabled by setting the corresponding enable bit.
Table 19.9 Receive Complete Interrupts and Error Interrupt
Interrupt Description
IBFI1 When IBFIE1 is set to 1 and IDR1 reception is completed
IBFI2 When IBFIE2 is set to 1 and IDR2 reception is completed
IBFI3 When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and
IBFIE3 are set to 1 and reception is completed up to TWR15
IBFI4 When IBFIE4 is set to 1 and IDR4 reception is completed
OBEI When OBEIE is set to 1 with OBEI set to 1.
ERRI When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
19.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,
HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15
The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 and the SCIF, while SMI, HIRQ6, HIRQ9, HIRQ10, and
HIRQ11 can be requested from LPC channel 2, 3, 4 or SCIF. HIRQ3, HIRQ4, HIRQ5, HIRQ7,
HIRQ8, HIRQ13, HIRQ14, and HIRQ15 are only for the SCIF.
There are two ways of clearing a host interrupt request when the LPC channels are used.
When the IEDIR bit in SIRQCR is cleared to 0, host interrupt sources and LPC channels are all
linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of
ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt
enable bit is automatically cleared to 0, and the host interrupt request is cleared.
When the IEDIR bit is set to 1 in SIRQCR, a host interrupt is requested by the only upon the host
interrupt enable bits. The host interrupt enable bit is not cleared when OBF is cleared. Therefore,
SMIE1, SMIE2, SMIE3A and SMIE3B, SMIE4, IRQ6En, IRQ9En, IRQ10En, and IRQ11En lose