Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 631 of 910
REJ09B0350-0300
R/W
Bit Bit Name Initial Value Slave Host Description
1 SMIE4 0 R/W ⎯ Host SMI Interrupt Enable 4
Enables or disables an SMI interrupt request when
OBF4 is set by an ODR4 write.
0: Host SMI interrupt request by OBF4 and SMIE4
is disabled
[Clearing conditions]
• Writing 0 to SMIE4
• LPC hardware reset, LPC software reset
• Clearing OBF4 to 0 (when IEDIR4 = 0)
1: [When IEDIR4 = 0]
Host SMI interrupt request by setting OBF4 to 1
is enabled
[When IEDIR4 = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE4 = 0
0 ⎯ 0 R/W ⎯ Reserved
The initial value should not be changed.
19.3.16 SERIRQ Control Register 3 (SIRQCR3)
SIRQCR3 contains bits that select the host interrupt request outputs.
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
4
3
2
1
0
SELIRQ15
SELIRQ14
SELIRQ13
SELIRQ8
SELIRQ7
SELIRQ5
SELIRQ4
SELIRQ3
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Host IRQ Interrupt Select
These bits select the state of the output on the
SERIRQ pins.
0: SERIRQ pin output is in the Hi-Z state
1: SERIRQ pin output is low