Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 620 of 910
REJ09B0350-0300
19.3.13 SERIRQ Control Register 0 (SIRQCR0)
SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
R/W
Bit Bit Name Initial Value Slave Host Description
7 Q/C 0 R ⎯ Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
• LPC hardware reset, LPC software reset
• Specification by SERIRQ transfer cycle stop
frame
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.
6 SELREQ 0 R/W ⎯ Start Frame Initiation Request Select
Selects the condition of a start frame initiation
request when a host interrupt request is cleared in
quiet mode.
0: Start frame initiation is requested when all
interrupt requests are cleared
1: Start frame initiation is requested when one or
more interrupt requests are cleared
5 IEDIR2 0 R/W ⎯ Interrupt Enable Direct Mode 2
Selects whether an SERIRQ interrupt generation of
LPC channel 2 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the enable
bit.
0: A host interrupt is generated when both the enable
bit and the corresponding OBF flag are set
1: A host interrupt is generated when the enable bit
is set