Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 614 of 910
REJ09B0350-0300
• STR1
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU17
DBU16
DBU15
DBU14
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3 C/D1 0 R R Command/Data
When the host writes to IDR1, bit 2 of the I/O
address is written into this bit to indicate whether
IDR1 contains data or a command.
0: Content of input data register (IDR1) is a data
1: Content of input data register (IDR1) is a
command
2 DBU12 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF1 0 R R Input Buffer Full
This bit is an internal interrupt source to the slave
(this LSI). The IBF1 flag setting and clearing
conditions are different when the fast Gate A20 is
used. For details, see table 19.5.
0: [Clearing condition]
When the slave reads IDR1
1: [Setting condition]
When the host writes to IDR1 in I/O write cycle
0 OBF1 0 R/(W)* R Output Buffer Full
0: [Clearing conditions]
• When the host reads ODR1 in I/O read cycle
• When the slave writes 0 to the OBF1 bit
1: [Setting condition]
When the slave writes to ODR1
Note: * Only 0 can be written to clear the flag.