Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 609 of 910
REJ09B0350-0300
19.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)
LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data
registers. The contents of the address fields in LADR3 must not be changed while channel 3 is
operating (while LPC3E is set to 1).
• LADR3H
R/W
Bit Bit Name Initial Value
Slave Host
Description
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel 3 Address Bits 15 to 8
Set the LPC channel 3 host address.
• LADR3L
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
Channel 3 Address Bits 7 to 3
Set the LPC channel 3 host address.
2 ⎯ 0 R/W ⎯ Reserved
The initial value should not be changed.
1 Bit 1 0 R/W ⎯ Channel 3 Address Bit 1
Sets the LPC channel 3 host address.
0 TWRE 0 R/W ⎯ Bidirectional Data Register Enable
Enables or disables bidirectional data register
operation.
0: TWR operation is disabled
TWR-related I/O address match determination is
halted
1: TWR operation is enabled