Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 608 of 910
REJ09B0350-0300
• LADR2L
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
4
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
Channel 2 Address Bits 7 to 3
Set the LPC channel 2 host address.
2 Bit 2 0 R/W ⎯ Reserved
This bit is ignored when an address match is decided.
1
0
Bit 1
Bit 0
1
0
R/W
R/W
⎯
⎯
Channel 2 Address Bits 1 and 0
Set the LPC channel 2 host address.
• Host select register
I/O Address
Bits 5 to 3 Bit 2 Bits 1 and 0
Transfer
Cycle Host Select Register
Bits 15 to 3 in LADR2 0 Bits 1 and 0 in LADR2 I/O write IDR2 write (data)
Bits 15 to 3 in LADR2 1 Bits 1 and 0 in LADR2 I/O write IDR2 write (command)
Bits 15 to 3 in LADR2 0 Bits 1 and 0 in LADR2 I/O read ODR2 read
Bits 15 to 3 in LADR2 1 Bits 1 and 0 in LADR2 I/O read STR2 read
Note: * When channel 2 is used, the content of LADR2 must be set so that the addresses for
channels 1, 3, 4, and SCIF are different.