Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 607 of 910
REJ09B0350-0300
• Host select register
I/O Address
Bits 5 to 3 Bit 2 Bits 1 and 0
Transfer
Cycle Host Select Register
Bits 15 to 3 in LADR1 0 Bits 1 and 0 in LADR1 I/O write IDR1 write (data)
Bits 15 to 3 in LADR1 1 Bits 1 and 0 in LADR1 I/O write IDR1 write (command)
Bits 15 to 3 in LADR1 0 Bits 1 and 0 in LADR1 I/O read ODR1 read
Bits 15 to 3 in LADR1 1 Bits 1 and 0 in LADR1 I/O read STR1 read
Note: * When channel 1 is used, the content of LADR1 must be set so that the addresses for
channels 2, 3, 4, and SCIF are different.
19.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)
LADR2 sets the LPC channel 2 host address. The LADR2 contents must not be changed while
channel 2 is operating (while LPC2E is set to 1).
• LADR2H
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel 2 Address Bits 15 to 8
Set the LPC channel 2 host address.