Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 605 of 910
REJ09B0350-0300
19.3.4 Host Interface Control Register 5 (HICR5)
HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 OBEIE 0 R/W ⎯ Output Buffer Empty Interrupt Enable
Enables or disables OBEI interrupts (for this LSI).
0: Output buffer empty interrupt request is disabled
1: Output buffer empty interrupt request is enabled
6 OBEI 0 R/W ⎯ Output Buffer Empty Interrupt Flag
0: [Clearing conditions]
• Writing 0 after reading OBEI = 1
• LPC hardware reset or LPC software reset
1: [Setting condition]
When one of OBF1, OBF2, OBF3A, OBF3B, and
OBF4 is cleared
5 to 4 ⎯ All 0 R/W ⎯ Reserved
The initial value bit should not be changed.
3 SCIFE 0 R/W ⎯ SCIF Enable
Enables or disables access from the LPC host of
the SCIF.
0: Disables access from the LPC host of the SCIF
1: Enables access from the LPC host of the SCIF
2 to 0 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be changed.