Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 602 of 910
REJ09B0350-0300
R/W
Bit Bit Name
Initial
Value
Slave Host Description
4 ABRT 0 R/(W)* ⎯ LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset
(LRESET pin falling edge detection)
• LPC software reset (LRSTB = 1)
• LPC hardware shutdown
(SDWNE = 1 and LPCPD pin falling edge
detection)
• LPC software shutdown (SDWNB = 1)
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
3 IBFIE3 0 R/W ⎯ IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register IDR3 and TWR receive
complete interrupt requests disabled
1: [When TWRE = 0 in LADR3]
Input data register (IDR3) receive complete
interrupt requests enabled
[When TWRE = 1 in LADR3]
Input data register (IDR3) and TWR receive
complete interrupt requests enabled
2 IBFIE2 0 R/W ⎯ IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled