Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 601 of 910
REJ09B0350-0300
R/W
Bit Bit Name
Initial
Value
Slave Host Description
0 LSCIB 0 R/W ⎯ LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit. For details, refer to description on the LSCIE bit in
HICR0.
19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 and the bit 7 in HICR2
monitor the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset.
The states of other bits are decided by the pin states. The pin states can be monitored by the pin
monitoring bits regardless of the LPC interface operating state or the operating state of the
functions that use pin multiplexing.
• HICR2
R/W
Bit Bit Name
Initial
Value
Slave Host
Description
7 GA20 Undefined R ⎯ GA20 Pin Monitor
6 LRST 0 R/(W)* ⎯ LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
5 SDWN 0 R/(W)* ⎯ LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
• Writing 0 after reading SDWN = 1
• LPC hardware reset
(LRESET pin falling edge detection)
• LPC software reset (LRSTB = 1)
1: [Setting condition]
LPCPD pin falling edge detection