Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 595 of 910
REJ09B0350-0300
19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
• HICR0
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
LPC3E
LPC2E
LPC1E
0
0
0
R/W
R/W
R/W
⎯
⎯
⎯
LPC Enables 3 to 1
Enable or disable the LPC interface function. When the
LPC interface is enabled (one of the three bits is set to
1), processing for data transfer between the slave (this
LSI) and the host is performed using pins LAD3 to
LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN,
and LPCPD.
• LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, or TWR0 to TWR15
1: LPC channel 3 operation is enabled
• LPC2E
0: LPC channel 2 operation is disabled
No address (LADR2) matches for IDR2, ODR2, or
STR2
1: LPC channel 2 operation is enabled
• LPC1E
0: LPC channel 1 operation is disabled
No address (LADR1) matches for IDR1, ODR1, or
STR1
1: LPC channel 1 operation is enabled