Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 593 of 910
REJ09B0350-0300
19.3 Register Descriptions
The LPC has the following registers.
Table 19.2 Register Configuration
R/W
Register Name Abbreviation Slave Host
Initial
Value
Address
Data Bus
Width
Host interface control register 0 HICR0 R/W ⎯ H'00 H'FE40 8
Host interface control register 1 HICR1 R/W ⎯ H'00 H'FE41 8
Host interface control register 2 HICR2 R/W ⎯ ⎯ H'FE42 8
Host interface control register 3 HICR3 R ⎯ ⎯ H'FE43 8
Host interface control register 4 HICR4 R/W ⎯ H'00 H'FDD9 8
Host interface control register 5 HICR5 R/W ⎯ H'00 H'FE33 8
LPC channel 1 address register H LADR1H R/W ⎯ H'00 H'FDC0 8
LPC channel 1 address register L LADR1L R/W ⎯ H'60 H'FDC1 8
LPC channel 2 address register H LADR2H R/W ⎯ H'00 H'FDC2 8
LPC channel 2 address register L LADR2L R/W ⎯ H'62 H'FDC3 8
LPC channel 3 address register H LADR3H R/W ⎯ H'00 H'FE34 8
LPC channel 3 address register L LADR3L R/W ⎯ H'00 H'FE35 8
LPC channel 4 address register H LADR4H R/W ⎯ H'00 H'FDD4 8
LPC channel 4 address register L LADR4L R/W ⎯ H'00 H'FDD5 8
Input data register 1 IDR1 R W H'00 H'FE38 8
Input data register 2 IDR2 R W H'00 H'FE3C 8
Input data register 3 IDR3 R W H'00 H'FE30 8
Input data register 4 IDR4 R W H'00 H'FDD6 8
Output data register 1 ODR1 R/W R H'00 H'FE39 8
Output data register 2 ODR2 R/W R H'00 H'FE3D 8
Output data register 3 ODR3 R/W R H'00 H'FE31 8
Output data register 4 ODR4 R/W R H'00 H'FDD7 8
Status register 1 STR1 R/W R H'00 H'FE3A 8
Status register 2 STR2 R/W R H'00 H'FE3E 8
Status register 3 STR3 R/W R H'00 H'FE32 8
Status register 4 STR4 R/W R H'00 H'FDD8 8