Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 592 of 910
REJ09B0350-0300
19.2 Input/Output Pins
Table 19.1 lists the LPC pin configuration.
Table 19.1 Pin Configuration
Name Abbreviation Port I/O Function
LPC address/
data 3 to 0
LAD3 to LAD0 P33 to P30 I/O Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
LPC frame LFRAME P34 Input*
1
Transfer cycle start and forced
termination signal
LPC reset LRESET P35 Input*
1
LPC interface reset signal
LPC clock LCLK P36 Input 33-MHz PCI clock signal
Serialized
interrupt request
SERIRQ P37 I/O*
1
Serialized host interrupt request
signal in synchronization with LCLK
LSCI general
output
LSCI PB1 Output*
1,
*
2
General output
LSMI general
output
LSMI PB0 Output*
1,
*
2
General output
PME general
output
PME P80 Output*
1,
*
2
General output
GATE A20 GA20 P81 Output*
1,
*
2
Gate A20 control signal output
LPC clock run CLKRUN P82 I/O*
1,
*
2
LCLK restart request signal when
serial host interrupt is requested
LPC power-down LPCPD P83 Input*
1
LPC module shutdown signal
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.