Datasheet

Section 18 Keyboard Buffer Control Unit (PS2)
Rev. 3.00 Sep. 28, 2009 Page 588 of 910
REJ09B0350-0300
18.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission
Figure 18.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the
automatic transmission. Switch to the KD output by the automatic transmission is performed when
KBTS is set to 1 and TXCR is not cleared to 0. In this case, the KD output by the KDO bit
(KBCRL) is masked.
Output switch signal
KBTS • (TXCR0 + TXCR1 + TXCR2 + TXCR3)
Output by KDO bit (KBCRL)
KD output
Output by automatic transmission
Figure 18.20 KDO Output
18.5.3 Module Stop Mode Setting
Keyboard buffer control unit operation can be enabled or disabled using the module stop control
register. The initial setting is for keyboard buffer control unit operation to be halted. Register
access is enabled by canceling module stop mode. For details, see section 24, Power-Down
Modes.
18.5.4 Medium-Speed Mode
In medium-speed mode, the PS2 operates with the medium-speed clock. For normal operation of
the PS2, set the medium-speed clock to a frequency of 300 kHz or higher.
18.5.5 Transmit Completion Flag (KBTE)
When TXCR3 to TXCR0 are 1011 (transmit completion notification) and then the TXCR3 to
TXCR0 are initialized by clearing KBIOE or KBTS to 0, the transmit completion flag (KBTE) is
set. In this case, KTER is invalid.