Datasheet

Section 18 Keyboard Buffer Control Unit (PS2)
Rev. 3.00 Sep. 28, 2009 Page 587 of 910
REJ09B0350-0300
18.5 Usage Notes
18.5.1 KBIOE Setting and KCLK Falling Edge Detection
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the
KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the
KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 18.19 shows the
timing of KBIOE setting and KCLK falling edge detection.
T1 T2
φ
KCLK (pin)
Internal KCLK
(KCLKI)
Falling edge
signal
KBIOE
KBFSEL
KBE
KBF
Figure 18.19 KBIOE Setting and KCLK Falling Edge Detection Timing