Datasheet

Section 18 Keyboard Buffer Control Unit (PS2)

Rev. 3.00 Sep. 28, 2009 Page 581 of 910

REJ09B0350-0300

18.4.7 Receive Timing

Figure 18.12 shows the receive timing.

N + 1 N + 2N

KCLK (pin)

KD (pin)

Internal

KCLK (KCLKI)

Falling edge

signal

RXCR3 to

RXCR0

Internal KD

(KDI)

KBBR7 to

KBBR0

φ*

Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode.

Figure 18.12 Receive Counter and KBBR Data Load Timing

18.4.8 Operation during Data Reception

If the KBS bit in KBCRH is set to 1 with other keyboard buffer control units in reception*, the

KCLK is automatically pulled down. Figure 18.13 shows receive timing and the KCLK.

Note: * Period from the first falling edge of KCLK to completion of reception (KBF = 1).

KCLK

KCLK for

other PS2

128910

0 1 7 Parity

Stop bit

Automatic I/O inhibit

Start bit

KBF

Figure 18.13 Receive Timing and KCLK