Datasheet

Section 18 Keyboard Buffer Control Unit (PS2)
Rev. 3.00 Sep. 28, 2009 Page 580 of 910
REJ09B0350-0300
18.4.6 KBF Setting Timing and KCLK Control
Figure 18.11 shows the KBF setting timing and the KCLK pin states.
φ*
Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode.
KCLK
(pin)
Internal
KCLK
Fallin
g edge
signal
RXCR3 to
RXCR0
KCLK
(output)
KBF
11th fall
Automatic I/O inhibit
B'0000B'1010
Figure 18.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing