Datasheet

Section 18 Keyboard Buffer Control Unit (PS2)
Rev. 3.00 Sep. 28, 2009 Page 576 of 910
REJ09B0350-0300
12
89
017
10 11
KCLK
(pin state)
KCLK
(input)
Receive
completed
notification
KCLK
(output)
KBTE
KTER
KBTS
KD
(pin state)
Parity
I/O inhibit
[1] to [3]
[6] [7] [8]
[9] [10] [11]
[4]
[5]
Stop bit
I/O inhibit
Start bit
Figure 18.6 Transmit Timing
18.4.3 Receive Abort
This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard
side) in the event of a protocol error, etc. In this case, the system holds the clock low. During
reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when
the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is
an abort request from the system, and data transmission from the keyboard is aborted. Thus the
system can abort reception by holding the clock low for a certain period. A sample receive abort
processing flowchart is shown in figure 18.7, and the receive abort timing in figure 18.8.