Datasheet

Section 18 Keyboard Buffer Control Unit (PS2)
Rev. 3.00 Sep. 28, 2009 Page 570 of 910
REJ09B0350-0300
18.3.4 Keyboard Control Register L (KBCRL)
KBCRL enables the receive counter count and controls the keyboard buffer control unit pin
output.
Bit Bit Name
Initial
Value R/W Description
7 KBE 0 R/W Keyboard Enable
Enables or disables loading of receive data into KBBR.
0: Loading of receive data into KBBR is disabled
1: Loading of receive data into KBBR is enabled
6 KCLKO 1 R/W Keyboard Clock Out
Controls PS2 clock I/O pin output.
0: PS2 clock I/O pin is low
1: PS2 clock I/O pin is high
5 KDO 1 R/W Keyboard Data Out
Controls PS2 data I/O pin output.
0: PS2 data I/O pin is low
1: PS2 data I/O pin is high
When the start bit (KDO) is automatically cleared
(KDO = 1) by means of automatic transmission, 0 is
written after reading 1.
4 — 1 — Reserved
This bit is always read as 1 and cannot be modified.