Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 555 of 910
REJ09B0350-0300
17.5 Interrupt Sources
The IIC has interrupt source IICI. Table 17.8 shows the interrupt sources and priority. Individual
interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the
interrupt controller independently.
The IIC interrupts are used as on-chip DTC activation sources.
Table 17.8 IIC Interrupt Sources
Channel Name Enable Bit Interrupt Source Interrupt Flag Priority
0 IICI0 IEIC I
2
C bus interface interrupt
request
IRIC High
1 IICI1 IEIC I
2
C bus interface interrupt
request
IRIC
2 IICI2 IEIC I
2
C bus interface interrupt
request
IRIC
Low
17.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
2
C bus, neither
condition will be output correctly.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing ICDR.
⎯ Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
⎯ Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 17.9 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.