Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 553 of 910
REJ09B0350-0300
17.4.8 Noise Canceller
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched
internally. Figure 17.21 shows a block diagram of the noise canceller.
The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
System clock
cycle
Sampling clock
C
DQ
Latch
C
DQ
Latch
SCL or
SDA input
signal
Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
Figure 17.21 Block Diagram of Noise Canceller
17.4.9 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in ICRES or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 17.3.7, I
2
C Bus
Control Initialization Register (ICRES).
(1) Scope of Initialization
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized: