Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 530 of 910
REJ09B0350-0300
17.3.8 I
2
C Bus Extended Control Register (ICXR)
ICXR enables or disables the I
2
C bus interface interrupt generation and handshake control, and
indicates the status of receive/transmit operations.
Bit Bit Name
Initial
Value
R/W Description
7 STOPIM 0 R/W Stop Condition Interrupt Source Mask
Enables or disables the interrupt generation when the
stop condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation
when the stop condition is detected (STOP = 1 or
ESTP = 1) in slave mode.
1: Disables IRIC flag setting and interrupt generation
when the stop condition is detected.
6 HNDS 0 R/W Enables or disables handshake control in receive mode
for the selection of reception with handshaking.
0: Disables handshake control
1: Enables handshake control
Note: When the IIC module is in use, be sure to set this
bit to 1.
When the HNDS bit is cleared to 0 and a round of
reception is completed with ICDRR empty (the ICDRF
flag is 0), successive reception will proceed with the
next round of reception. At the same time, a clock is
continuously supplied over the SCL line.
In this case, the sequence of operations should be
such that unnecessary clock cycles are not output to
the bus after reception of the last of the data.
When the HNDS bit is set to 1, SCL is fixed low and
clock output stops on completion of reception. SCL is
released and reception of the next frame is enabled by
reading the receive data from ICDR.