Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 525 of 910
REJ09B0350-0300
17.3.6 I
2
C Bus Status Register (ICSR)
ICSR consists of status flags. Also see tables 17.5 and 17.6.
Bit Bit Name
Initial
Value
R/W Description
7 ESTP 0 R/(W)* Error Stop Condition Detection Flag
This bit is valid in I
2
C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
• When 0 is written in ESTP after reading ESTP = 1
• When the IRIC flag in ICCR is cleared to 0
6 STOP 0 R/(W)* Normal Stop Condition Detection Flag
This bit is valid in I
2
C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer
completion.
[Clearing conditions]
• When 0 is written in STOP after reading STOP = 1
• When the IRIC flag is cleared to 0
5 IRTR 0 R/(W)* I
2
C Bus Interface Continuous Transfer Interrupt
Request Flag
Indicates that the I
2
C bus interface has issued an
interrupt request to the CPU, and the source is
completion of reception/transmission of one frame.
When the IRTR flag is set to 1, the IRIC flag is also set
to 1 at the same time.
[Setting conditions]
I
2
C bus format slave mode:
• When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
Master mode or clocked synchronous serial format
mode with I
2
C bus format:
• When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
• When 0 is written after reading IRTR = 1
• When the IRIC flag is cleared to 0 while ICE is 1