Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 519 of 910
REJ09B0350-0300
Bit Bit Name
Initial
Value
R/W Description
1 IRIC 0 R/(W)* I
2
C Bus Interface Interrupt Request Flag
Indicates that the I
2
C bus interface has issued an
interrupt request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
See section 17.4.7, IRIC Setting Timing and SCL
Control. The conditions under which IRIC is set also
differ depending on the setting of the ACKE bit in
ICCR.
[Setting conditions]
All operating modes:
1. When a start condition is detected in transmit mode
and the ICDRE flag is set to 1
2. When data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1
3. When data is transferred from ICDRS to ICDRR in
receive mode and the ICDRF flag is set to 1
4. If 1 is received as the acknowledge bit (when the
ACKE bit is 1 in transmit mode) at the completion of
data transmission
I
2
C bus format master mode:
1. When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1
2. When the AL flag is set to 1 after bus arbitration is
lost while the ALIE bit is 1
I
2
C bus format slave mode:
1. When the slave address (SVA or SVAX) matches
after the reception of the first frame following the
start condition and the AAS flag or AASX flag is set
to 1
2. When the general call address is detected after the
reception of the first frame following the start
condition and the ADZ flag is set to 1 (the FS bit in
SAR is 0)
3. When a stop condition is detected (when the STOP
or ESTP flag is set to 1) while the STOPIM bit is 0