Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 508 of 910
REJ09B0350-0300
17.3 Register Descriptions
The I
2
C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see
section 3.2.3, Serial Timer Control Register (STCR).
Table 17.2 Register Configuration
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data Bus
Width
I
2
C bus extended control register_0 ICXR_0 R/W H'00 H'FED4 8
I
2
C bus control register_0 ICCR_0 R/W H'01 H'FFD8 8
I
2
C bus status register_0 ICSR_0 R/W H'00 H'FFD9 8
I
2
C bus data register_0 ICDR_0 R/W ⎯ H'FFDE 8
Second slave address register_0 SARX_0 R/W H'01 H'FFDE 8
I
2
C bus mode register_0 ICMR_0 R/W H'00 H'FFDF 8
Slave address register_0 SAR_0 R/W H'00 H'FFDF 8
Channel 0
I
2
C bus control initialization
register_0
ICRES_0 R/W H'0F H'FEE6 8
I
2
C bus extended control register_1 ICXR_1 R/W H'00 H'FED5 8
I
2
C bus control register_1 ICCR_1 R/W H'01 H'FF88
H'FED0*
8
I
2
C bus status register_1 ICSR_1 R/W H'00 H'FF89
H'FED1*
8
I
2
C bus data register_1 ICDR_1 R/W ⎯ H'FF8E
H'FECE*
8
Second slave address register_1 SARX_1 R/W H'01 H'FF8E
H'FECE*
8
Channel 1
I
2
C bus mode register_1 ICMR_1 R/W H'00 H'FF8F
H'FECF*
8
Slave address register_1 SAR_1 R/W H'00 H'FF8F
H'FECF*
8