Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 500 of 910
REJ09B0350-0300
Table 16.8 shows the range of initialization of the registers related to data transmission/reception
through the LPC interface, making a classification by each mode.
Table 16.8 Register States
Register
System
Reset
SCIFRST REGRST
LPC
Reset
LPC
Shutdown
LPC
Abort
SCIFADRH Bits 15 to 8 Initialized Retained Retained Retained Retained Retained
SCIFADRL Bits 7 to 0 Initialized Retained Retained Retained Retained Retained
HICR5 SCIFE Initialized Retained Retained Retained Retained Retained
SIRQCR4 Bits 7 to 4,
SCSIRQ3 to 0
Initialized Retained Retained Retained Retained Retained
SCIFCR SCIFOE1,
SCIFOE0,
OUT2LOOP,
CKSEL1,
CKSEL0,
SCIFRST,
REGRST
Initialized Retained Retained Retained Retained Retained
FRBR Bits 7 to 0 Initialized Retained Initialized Initialized Retained Retained
FTHR Bits 7 to 0 Initialized Retained Initialized Initialized Retained Retained
FDLL Bits 7 to 0 Initialized Retained Initialized Initialized Retained Retained
FDLH Bits 7 to 0 Initialized Retained Initialized Initialized Retained Retained
FIIR FIFOE1,
FIFOE0, INTID2
to INTID0,
INTPEND
Initialized Retained Initialized Initialized Retained Retained
FFCR RCVRTRIG1,
RCVRTRIG0,
XMITFRST,
RCVRFRST,
FIFOE
Initialized Retained Initialized Initialized Retained Retained
FLCR DLAB, TREAK,
EPS, PEN,
STOP, CLS1,
CLS0
Initialized Retained Initialized Initialized Retained Retained