Datasheet
Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 8 of 910
REJ09B0350-0300
1.3 Block Diagram
P
A
0
/
K
IN
8
/PS
2
D
C
P
A
1
/K
IN9
/PS
2
D
D
P
A
2
/
K
IN
1
0
/PS
2
A
C
P
A3
/K
IN1
1
/PS
2
A
D
P
A
4
/
K
IN
1
2
/P
S
2
B
C
P
A
5
/
K
IN1
3
/P
S
2
B
D
P
A
6
/K
IN1
4
/PS2
C
C
P
A
7
/K
IN
1
5
/PS
2
C
D
P20
P2
1
P22
P23
P24
P25
P
2
6
P
2
7
P10
P1
1
P1
2
P13
P14
P15
P16
P17
P
3
0
/
L
AD
0
P
3
1
/LA
D
1
P
3
2
/L
A
D
2
P
3
3
/L
A
D3
P
3
4
/L
F
R
A
M
E
P
3
5
/
L
R
E
S
E
T
P36
/L
CL
K
P
3
7
/S
E
R
IR
Q
P
B
0
/
L
S
M
I
P
B
1
/L
S
CI
P
B
2
/
R
I/PW
M
U
0
B
P
B
3
/
D
C
D
/PW
M
U
1
B
P
B
4
/DSR
P
B
5
/
D
T
R
P
B
6
/CTS
P
B7/
R
T
S
PC0
/
T
I
O
CA0
/
W
U
E
8
P
C
1
/TIOC
B
0
/
W
UE9
PC
2
/TIOC
C0
/TCLKA/W
U
E
1
0
P
C
3
/
T
IOC
D0/
T
CL
K
B/W
UE
1
1
PC4
/T
I
O
CA1
/W
U
E
1
2
P
C
5
/TIOC
B1/
T
CLK
C
/
W
UE
1
3
P
C6
/T
I
O
CA2
/W
UE
1
4
P
C
7
/TIOC
B
2
/TCLK
D
/
W
U
E
1
5
P50
/
F
T
xD
P
5
1
/FR
x
D
P52
/
S
CL0
RAM
I
n
te
rru
p
t co
n
tro
lle
r
8
-b
i
t t
imer
(
4
c
h
a
n
n
e
l
s)
ROM
(fla
s
f memo
r
y)
Clo
c
k p
u
l
se
ge
n
e
r
ato
r
H8S/260
0
CPU
W
DT
(2
ch
a
n
n
e
l
s)
P
S
2
(4 ch
a
n
n
e
l
s)
S
CI
F
(
1
ch
a
n
n
e
l
)
1
6
-b
i
t TD
P
(3
ch
a
n
n
e
l
s)
1
6
-b
i
t
T
CM
(4 ch
a
n
n
e
l
s)
S
C
I (2 ch
a
n
n
e
l
s)
S
m
a
rt Card
I/F
(2
c
h
a
n
n
e
l
s)
8
-b
i
t
P
W
M
(
1
2
ch
a
n
n
e
l
s)
IIC
(
3
c
h
a
n
n
e
l
s)
1
4
-b
i
t PW
M
(2
ch
a
n
n
e
l
s)
1
6
-b
i
t T
P
U
(3 ch
a
n
n
e
l
s)
1
0
-b
i
t
A
/
D
co
n
v
e
rte
r
(16
ch
a
n
n
e
l
s)
R
E
S
XTAL
EXTAL
MD
2
MD
1
NMI
ETRS
T
VC
C
VC
C
VC
C
VCL
VS
S
VS
S
VS
S
VS
S
VS
S
AVref
AVCC
A
VSS
L
P
C
(4 ch
a
n
n
e
l
s)
H-UDI
P
8
0
/PME
P
8
1
/
G
A
2
0
P
8
2
/CL
K
R
UN
P
8
3
/L
P
C
P
D
P
8
4
/T
x
D
1
/
IRQ3
P
8
5
/RxD
1
/
IR
Q4
P
8
6
/
S
CK
1
/S
CL
1
/
I
R
Q5
P
4
0
/
T
MI0
/
T
xD
2
/T
C
MCYI
0
P
4
1
/TMO0
/
R
x
D
2
/TC
MCKI0
/
T
C
M
M
C
I
0
P
4
2
/
S
DA1
/T
C
MCYI1
P43
/TM
I
1
/S
CK2/
T
CMCK
I
1
/
T
CM
MCI1
P
4
4
/
T
MO1
/PW
M
U
2
B/T
C
MC
YI2
P4
5
/P
W
M
U
3
B/T
CMC
K
I
2
/T
CMMC
I2
P
4
6
/PWX0
/PW
M
U
4
B
/T
CMCY
I3
P47
/PWX1/PW
M
U
5
B
/TC
MCKI3/TC
M
M
C
I
3
P
6
0
/
K
IN
0
P61
/
K
IN1
P
6
2
/K
IN
2
P
6
3
/
K
IN3
P
6
4
/K
IN4
P
6
5
/K
IN
5
P
6
6
/
IRQ
6
/K
IN6
P67
/
IRQ7
/
K
IN
7
P
9
0
/
IRQ2
P
9
1
/
IR
Q1
P92
/
IRQ
0
P
9
3
/I
R
Q12
P
9
4
/
IRQ
1
3
P
9
5
/IRQ14
P
9
6
/φ
/EX
CL
P
9
7
/IRQ
1
5
/S
D
A
0
PE0
/
E
xEX
CL
P
E1*
1
/ET
CK
P
E
2
*
1
/ET
DI
P
E
3
*
1
/ET
DO
P
E
4
*
1
/ET
M
S
Port 8
P
G
0
/
ExIRQ
8
/T
M
I
X
/TDPCYI1
P
G1/E
xIR
Q9
/
T
MIY
/T
DP
C
K
I
1
/
T
DPMCI1
P
G
2
/E
x
IRQ
1
0
/
S
DA2
P
G3/E
x
I
R
Q11
/S
CL
2
P
G4/
E
x
IR
Q1
2
/E
xS
DAA
P
G
5
/ExIRQ13
/E
x
S
CLA
P
G6
/
E
xIR
Q14
/ExS
DA
B
PG7
/E
x
IRQ
1
5
/
E
x
S
CLB
P
I
0
*
2
PI1
*
2
P
I2*
2
P
I3
*
2
P
I4*
2
P
I
5
*
2
PI6
*
2
P
I7*
2
PJ0*
2
PJ1
*
2
P
J
2
*
2
P
J3
*
2
P
J
4
*
2
PJ5
*
2
P
J
6
*
2
P
J
7
*
2
P
F
0
/PW
M
U
0
A
/
IRQ8
P
F
1
/PW
M
U
1
A
/
IR
Q9
P
F
2
/TM
OY/
IRQ
1
0
/TDPCY
I
0
P
F
3
/
T
MO
X
/IRQ11
/T
DP
C
K
I
0
/
T
DPMCI0
PF4
/P
W
M
U
2
A
P
F
5
/P
W
M
U
3
A
PF6
/P
W
M
U
4
A
P
F
7
/PW
M
U
5
A
Port B
Port A
Port 9
P
H0/
E
x
IR
Q6
/T
DPCYI2
PH1
/ExIRQ7/TD
P
CKI2/TD
PMC
I2
P
H2
P
H3
P
H4
P
H5
Notes: 1. Not supported by the system development tool (emulator)
2. Not supported by TFP-144 V and TLP-145 V
PD0/AN8
PD1/AN9
PD2AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
Port J
Address bus
Data bus
Bus controller
Internal address bus
Internal Data bus
Port IPort HPort GPort FPort EPort C
Port 2 Port 1Port 3Port 4Port 5Port 6Port 7Port D
Figure 1.2 Internal Block Diagram